nb/intel/haswell: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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@ -22,6 +22,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "haswell.h"
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#include <southbridge/intel/lynxpoint/pch.h>
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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@ -69,3 +70,59 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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return current;
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}
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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struct device *const igfx_dev = dev_find_slot(0, PCI_DEVFN(2, 0));
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const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
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const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
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const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
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const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
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/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
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if (igfx_dev && igfx_dev->enabled && gfxvtbar
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&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
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current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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/* VTVC0BAR has to be set, enabled, and in 32-bit space */
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if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current,
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DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
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current += acpi_create_dmar_drhd_ds_ioapic(current,
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2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
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size_t i;
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for (i = 0; i < 8; ++i)
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current += acpi_create_dmar_drhd_ds_msi_hpet(current,
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0, PCH_HPET_PCI_BUS,
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PCH_HPET_PCI_SLOT, i);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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return current;
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}
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unsigned long northbridge_write_acpi_tables(struct device *const dev,
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unsigned long current,
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struct acpi_rsdp *const rsdp)
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{
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/* Create DMAR table only if we have VT-d capability. */
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const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
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if (capid0_a & VTD_DISABLE)
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return current;
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acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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return current;
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}
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@ -212,6 +212,14 @@ void dump_mem(unsigned start, unsigned end);
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void report_platform_info(void);
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#endif /* !__SMM__ */
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#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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struct acpi_rsdp;
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unsigned long northbridge_write_acpi_tables(device_t device,
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unsigned long start, struct acpi_rsdp *rsdp);
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#endif
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#endif
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#endif
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#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */
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@ -85,6 +85,7 @@ static struct device_operations pci_domain_ops = {
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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.write_acpi_tables = northbridge_write_acpi_tables,
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};
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static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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