nb/intel/haswell: Generate ACPI DMAR table

If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.

Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
This commit is contained in:
Matt DeVillier 2018-03-04 01:41:23 -06:00 committed by Patrick Georgi
parent 62bef5a6be
commit 85d98d9236
3 changed files with 66 additions and 0 deletions

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@ -22,6 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "haswell.h"
#include <southbridge/intel/lynxpoint/pch.h>
unsigned long acpi_fill_mcfg(unsigned long current)
{
@ -69,3 +70,59 @@ unsigned long acpi_fill_mcfg(unsigned long current)
return current;
}
static unsigned long acpi_fill_dmar(unsigned long current)
{
struct device *const igfx_dev = dev_find_slot(0, PCI_DEVFN(2, 0));
const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
if (igfx_dev && igfx_dev->enabled && gfxvtbar
&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current);
}
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_drhd_ds_ioapic(current,
2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
size_t i;
for (i = 0; i < 8; ++i)
current += acpi_create_dmar_drhd_ds_msi_hpet(current,
0, PCH_HPET_PCI_BUS,
PCH_HPET_PCI_SLOT, i);
acpi_dmar_drhd_fixup(tmp, current);
}
return current;
}
unsigned long northbridge_write_acpi_tables(struct device *const dev,
unsigned long current,
struct acpi_rsdp *const rsdp)
{
/* Create DMAR table only if we have VT-d capability. */
const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
if (capid0_a & VTD_DISABLE)
return current;
acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
printk(BIOS_DEBUG, "ACPI: * DMAR\n");
acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
current += dmar->header.length;
current = acpi_align_current(current);
acpi_add_table(rsdp, dmar);
return current;
}

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@ -212,6 +212,14 @@ void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(device_t device,
unsigned long start, struct acpi_rsdp *rsdp);
#endif
#endif
#endif
#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */

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@ -85,6 +85,7 @@ static struct device_operations pci_domain_ops = {
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
.write_acpi_tables = northbridge_write_acpi_tables,
};
static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)