From 85dc0d8daedc496435bba8c4c2a740b70f97ae9c Mon Sep 17 00:00:00 2001 From: Tobias Diedrich Date: Sat, 25 Nov 2017 22:25:16 +0100 Subject: [PATCH] intel/bd82x6x: Fix a small mistake in DIR_ROUTE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The register is 16-bits wide. If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten. See page 407ff on the Intel C216 datasheet, which says "Size: 16bits" with "Default: 3210h" for all DnnIR registers. This also makes sense given the register offsets: 3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W [3142h would be D30IR] 3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W 314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W 3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W [discontinuity in register addresses here] 315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W [315Eh would be D21IR] 3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Signed-off-by: Tobias Diedrich Reviewed-on: https://review.coreboot.org/22621 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/bd82x6x/pch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 51f3b94239..83d9d8d1dd 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -418,7 +418,7 @@ int rtc_failure(void); #define SOFT_RESET_DATA 0x38f8 #define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */