GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/apollolake: remove _RMV and _DSW methods from xhci.asl 

Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14966
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Hannah Williams 2016-05-25 11:12:43 -07:00 committed by Martin Roth
parent d6463dd42c
commit 85e3c77226
1 changed files with 6 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/soc/intel/apollolake/acpi/xhci.asl
View File

@ -1,4 +1,5 @@
/* This file is part of the coreboot project. /*
* This file is part of the coreboot project.
* *
* Copyright (C) 2016 Intel Corporation. * Copyright (C) 2016 Intel Corporation.
* *
@ -14,28 +15,17 @@
/* XHCI Controller 0:15.0 */ /* XHCI Controller 0:15.0 */
Device (XHC1) { Device (XHC1) {
Name(_ADR, 0x00150000) // Device 21, Function 0 Name (_ADR, 0x00150000) /* Device 21, Function 0 */
Name (_S3D, 3) /* D3 supported in S3 */ Name (_S3D, 3) /* D3 supported in S3 */
Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S0W, 3) /* D3 can wake device in S0 */
Name (_S3W, 3) /* D3 can wake system from S3 */ Name (_S3W, 3) /* D3 can wake system from S3 */
// Declare XHCI GPE status and enable bits are bit 13 /* Declare XHCI GPE status and enable bits are bit 13 */
Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 })
Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake
{
Return (Zero)
}
Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}
Method (_STA, 0) Method (_STA, 0)
{ {
Return (0xF) Return (0xF)
} }
} }