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mb/google/var/anahera4es: Add gpios to lock 

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
Also fix the gpio order of GPP_F19.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
anahera4es boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-07 15:02:17 +08:00 committed by Felix Held
parent 8dd1763bef
commit 85ec4e2a74
1 changed files with 12 additions and 13 deletions
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25
src/mainboard/google/brya/variants/anahera4es/gpio.c
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@ -21,17 +21,17 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_A22, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
/* B5 : ISH_I2C0_SDA ==> NC */
PAD_NC(GPP_B5, NONE),
PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
/* B6 : ISH_I2C0_SCL ==> NC */
PAD_NC(GPP_B6, NONE),
PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
/* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE),
PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE),
@ -39,21 +39,21 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_C4, NONE),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D5 : SRCCLKREQ0# ==> NC */
PAD_NC(GPP_D5, NONE),
/* D7 : SRCCLKREQ2# ==> NC */
PAD_NC(GPP_D7, NONE),
/* D13 : ISH_UART0_RXD ==> NC */
PAD_NC(GPP_D13, NONE),
PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> NC */
PAD_NC(GPP_D14, NONE),
PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
/* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC(GPP_D16, NONE),
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* D17 : UART1_RXD ==> NC */
PAD_NC(GPP_D17, NONE),
PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
PAD_CFG_GPO(GPP_E0, 1, PLTRST),
@ -63,14 +63,13 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E7, NONE),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP),
/* E23 : DDPA_CTRLDATA ==> NC */
PAD_NC(GPP_E23, NONE),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* F20 : EXT_PWR_GATE# ==> NC */
PAD_NC(GPP_F20, NONE),