soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE

This change splits the size of the console transfer region and size of
the bootblock/romstage Pre-RAM console region. This allows having a
larger Pre-RAM console while not impacting the size of the PSP verstage
console.

Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in
`setup_cbmem_console`, I chose to use the offsets provided in the
transfer buffer. It would be nice to eventually do this for all the
fields in the transfer buffer.

BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are no longer truncated

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>

src/soc/amd/cezanne/Kconfig

@@ -128,6 +128,12 @@ config PSP_SHAREDMEM_SIZE
 	  started.  The workbuf's base depends on the address of the reset
 	  vector.
 
+config PRE_X86_CBMEM_CONSOLE_SIZE
+	hex
+	default 0x1600
+	help
+	  Size of the CBMEM console used in PSP verstage.
+
 config PRERAM_CBMEM_CONSOLE_SIZE
 	hex
 	default 0x1600

src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc

@@ -12,7 +12,13 @@
 #endif
 
 	ALIGN_COUNTER(64)
-	PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
+#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)
+#if ENV_SEPARATE_VERSTAGE
+	PRERAM_CBMEM_CONSOLE(., CONFIG_PRE_X86_CBMEM_CONSOLE_SIZE)
+#else
+	REGION(cbmemc_transfer, ., CONFIG_PRE_X86_CBMEM_CONSOLE_SIZE, 4)
+#endif /* ENV_SEPARATE_VERSTAGE */
+#endif /* CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) */
 	TIMESTAMP(., TIMESTAMP_BUFFER_SIZE)
 	CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
 	FMAP_CACHE(., FMAP_SIZE)

src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld

@@ -27,6 +27,9 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE;
  *                     |                                |
  *                     |      cbfs_cache (if reqd)      |
  *                     |        (CBFS_CACHE_SIZE)       |
+ *                     +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
+ *                     |      Preram CBMEM console      |
+ *                     |   (PRERAM_CBMEM_CONSOLE_SIZE)  |
  *                     +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE
  *                     |                                |
  *                     |       verstage (if reqd)       |
@@ -48,11 +51,11 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE;
  *                     |     FMAP cache (FMAP_SIZE)     |
  *                     +--------------------------------+
  *                     | CBFS mcache (CBFS_MCACHE_SIZE) |
- *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRE_X86_CBMEM_CONSOLE_SIZE + 0x200
  *                     |  Early Timestamp region (512B) |
- *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
+ *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRE_X86_CBMEM_CONSOLE_SIZE
- *                     |      Preram CBMEM console      |
+ *                     |   PSP Verstage CBMEM console   |
- *                     |   (PRERAM_CBMEM_CONSOLE_SIZE)  |
+ *                     |  (PRE_X86_CBMEM_CONSOLE_SIZE)  |
  *                     +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE
  *                     |   PSP shared (vboot workbuf)   |
  *                     |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE)      |
@@ -99,6 +102,8 @@ SECTIONS
 	VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
 #endif
 
+        PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
+
 #if CONFIG_CBFS_CACHE_SIZE > 0
         . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
         CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE)

src/soc/amd/common/vboot/vboot_bootblock.c

@@ -2,6 +2,7 @@
 
 #include <amdblocks/reset.h>
 #include <bootblock_common.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <pc80/mc146818rtc.h>
 #include <security/vboot/vbnv.h>
@@ -61,6 +62,31 @@ void show_psp_transfer_info(void)
 	}
 }
 
+static void setup_cbmem_console(const struct transfer_info_struct *info)
+{
+
+	void *cbmemc;
+	size_t cbmemc_size;
+
+	if (info->console_offset < sizeof(*info))
+		return;
+
+	if (info->timestamp_offset <= info->console_offset)
+		return;
+
+	cbmemc_size = info->timestamp_offset - info->console_offset;
+
+	if (info->console_offset + cbmemc_size > info->buffer_size)
+		return;
+
+	cbmemc = (void *)((uintptr_t)info + info->console_offset);
+
+	/* We need to manually initialize cbmemc so we can fill the new buffer. cbmemc_init()
+	 * will also be called later in console_hw_init(), but it will be a no-op. */
+	cbmemc_init();
+	cbmemc_copy_in(cbmemc, cbmemc_size);
+}
+
 void boot_with_psp_timestamp(uint64_t base_timestamp)
 {
 	const struct transfer_info_struct *info = (const struct transfer_info_struct *)
@@ -69,6 +95,8 @@ void boot_with_psp_timestamp(uint64_t base_timestamp)
 	if (!transfer_buffer_valid(info) || info->timestamp == 0)
 		return;
 
+	setup_cbmem_console(info);
+
 	/*
 	 * info->timestamp is PSP's timestamp (in microseconds)
 	 * when x86 processor is released.

src/soc/amd/picasso/Kconfig

@@ -138,6 +138,12 @@ config PSP_SHAREDMEM_SIZE
 	  started.  The workbuf's base depends on the address of the reset
 	  vector.
 
+config PRE_X86_CBMEM_CONSOLE_SIZE
+	hex
+	default 0x1600
+	help
+	  Size of the CBMEM console used in PSP verstage.
+
 config PRERAM_CBMEM_CONSOLE_SIZE
 	hex
 	default 0x1600