From 863efe45459a836bcb1115901e832d0a41e0b433 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Tue, 15 Jun 2021 12:59:57 +0200
Subject: [PATCH] nb/intel/haswell: Move MRC glue code into a subfolder

Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future
commits will move the Broadwell MRC/refcode glue code to be in Haswell
northbridge scope, so plan in advance.

Tested on Asrock B85M Pro4, still boots.

Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/haswell/Makefile.inc               | 9 ++-------
 src/northbridge/intel/haswell/haswell_mrc/Makefile.inc   | 9 +++++++++
 .../intel/haswell/{ => haswell_mrc}/pei_data.h           | 0
 .../intel/haswell/{ => haswell_mrc}/raminit.c            | 4 ++--
 4 files changed, 13 insertions(+), 9 deletions(-)
 create mode 100644 src/northbridge/intel/haswell/haswell_mrc/Makefile.inc
 rename src/northbridge/intel/haswell/{ => haswell_mrc}/pei_data.h (100%)
 rename src/northbridge/intel/haswell/{ => haswell_mrc}/raminit.c (99%)

diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index f718f9a1af..2d1532be05 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -13,17 +13,12 @@ ramstage-y += acpi.c
 ramstage-y += minihd.c
 
 romstage-y += memmap.c
-romstage-y += raminit.c
 romstage-y += romstage.c
 romstage-y += early_init.c
 romstage-y += report_platform.c
 
-# We don't ship that, but booting without it is bound to fail
-cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
-mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
-mrc.bin-position := 0xfffa0000
-mrc.bin-type := mrc
-
 postcar-y += memmap.c
 
+subdirs-y += haswell_mrc
+
 endif
diff --git a/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc b/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc
new file mode 100644
index 0000000000..bd6314cc01
--- /dev/null
+++ b/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += raminit.c
+
+# We don't ship that, but booting without it is bound to fail
+cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
+mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
+mrc.bin-position := 0xfffa0000
+mrc.bin-type := mrc
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h
similarity index 100%
rename from src/northbridge/intel/haswell/pei_data.h
rename to src/northbridge/intel/haswell/haswell_mrc/pei_data.h
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
similarity index 99%
rename from src/northbridge/intel/haswell/raminit.c
rename to src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 45377839bc..338b4d0c41 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -14,6 +14,8 @@
 #include <device/pci_ops.h>
 #include <device/dram/ddr3.h>
 #include <northbridge/intel/haswell/chip.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
 #include <smbios.h>
 #include <spd.h>
 #include <security/vboot/vboot_common.h>
@@ -23,9 +25,7 @@
 #include <timestamp.h>
 #include <types.h>
 
-#include "raminit.h"
 #include "pei_data.h"
-#include "haswell.h"
 
 #define MRC_CACHE_VERSION 1