sb/intel/i82801jx/Makefile.inc: Sort entries
Sort them by stage execution order, then alphabetically. Place more complex rules at the end. Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42648 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -5,23 +5,23 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y)
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bootblock-y += bootblock.c
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bootblock-y += early_init.c
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ramstage-y += i82801jx.c
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romstage-y += early_init.c
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romstage-y += early_smbus.c
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ramstage-y += fadt.c
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ramstage-y += pci.c
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ramstage-y += lpc.c
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ramstage-y += pcie.c
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ramstage-y += usb_ehci.c
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ramstage-y += sata.c
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ramstage-y += hdaudio.c
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ramstage-y += thermal.c
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ramstage-y += i82801jx.c
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ramstage-y += lpc.c
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ramstage-y += pci.c
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ramstage-y += pcie.c
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ramstage-y += sata.c
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ramstage-y += smbus.c
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ramstage-y += thermal.c
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ramstage-y += usb_ehci.c
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ramstage-y += ../common/pciehp.c
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
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smm-y += smihandler.c
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romstage-y += early_init.c
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romstage-y += early_smbus.c
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endif
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