Removal of i82801DB (ICH4)
There are no boards that use the i82801DB (ICH4). The code does NOT work. Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
Ed Swierk
parent
c4e052cd50
commit
868de9838c
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@ -1,11 +0,0 @@
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config chip.h
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driver i82801db.o
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driver i82801db_uhci.o
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driver i82801db_lpc.o
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driver i82801db_ide.o
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driver i82801db_ehci.o
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driver i82801db_smbus.o
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driver i82801db_pci.o
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driver i82801db_ac97.o
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object i82801db_watchdog.o
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object i82801db_reset.o
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@ -1,55 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef I82801DB_CHIP_H
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#define I82801DB_CHIP_H
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struct southbridge_intel_i82801db_config
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{
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#define ICH5R_GPIO_USE_MASK 0x03
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#define ICH5R_GPIO_USE_DEFAULT 0x00
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#define ICH5R_GPIO_USE_AS_NATIVE 0x01
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#define ICH5R_GPIO_USE_AS_GPIO 0x02
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#define ICH5R_GPIO_SEL_MASK 0x0c
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#define ICH5R_GPIO_SEL_DEFAULT 0x00
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#define ICH5R_GPIO_SEL_OUTPUT 0x04
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#define ICH5R_GPIO_SEL_INPUT 0x08
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#define ICH5R_GPIO_LVL_MASK 0x30
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#define ICH5R_GPIO_LVL_DEFAULT 0x00
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#define ICH5R_GPIO_LVL_LOW 0x10
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#define ICH5R_GPIO_LVL_HIGH 0x20
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#define ICH5R_GPIO_LVL_BLINK 0x30
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#define ICH5R_GPIO_INV_MASK 0xc0
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#define ICH5R_GPIO_INV_DEFAULT 0x00
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#define ICH5R_GPIO_INV_OFF 0x40
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#define ICH5R_GPIO_INV_ON 0x80
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/* GPIO use select */
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unsigned char gpio[64];
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unsigned int pirq_a_d;
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unsigned int pirq_e_h;
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int enable_native_ide;
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};
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extern struct chip_operations southbridge_intel_i82801db_ops;
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#endif /* I82801DB_CHIP_H */
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@ -1,34 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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//kind of cmos_err for ich5
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#define RTC_FAILED (1 <<2)
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#define GEN_PMCON_3 0xa4
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static void check_cmos_failed(void)
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{
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uint8_t byte;
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byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
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if( byte & RTC_FAILED){
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//clear bit 1 and bit 2
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byte = cmos_read(RTC_BOOT_BYTE);
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byte &= 0x0c;
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byte |= MAX_REBOOT_CNT << 4;
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cmos_write(byte, RTC_BOOT_BYTE);
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}
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}
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@ -1,64 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "i82801db.h"
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void i82801db_enable(device_t dev)
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{
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device_t lpc_dev;
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uint16_t word;
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printk_debug("Entering %s\n", __FUNCTION__);
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/* See if we are behind the i82801db pci bridge
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lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
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*/
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lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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if (!lpc_dev) {
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return;
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}
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word = 0x0040;
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pci_write_config16(lpc_dev, 0xf2, word);
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/*
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if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
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index = dev->path.u.pci.devfn & 7;
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}
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else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
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index = (dev->path.u.pci.devfn & 7) +8;
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}
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reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
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reg &= ~(1 << index);
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if (!dev->enabled) {
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reg |= (1 << index);
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}
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if (reg != reg_old) {
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printk_debug("Trying to enable device, [0:1f:0] reg 0xf2 <- %04x\n", reg);
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pci_write_config16(lpc_dev, 0xf2, reg);
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}
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*/
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}
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struct chip_operations southbridge_intel_i82801db_ops = {
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CHIP_NAME("Intel 82801DB Southbridge")
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.enable_dev = i82801db_enable,
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};
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "i82801db.h"
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static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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/* Write the subsystem vendor and device id */
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = ac97_set_subsystem,
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};
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static struct device_operations ac97_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = 0,
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.scan_bus = 0,
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.enable = i82801db_enable,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver ac97_audio_driver __pci_driver = {
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.ops = &ac97_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
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};
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static const struct pci_driver ac97_modem_driver __pci_driver = {
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.ops = &ac97_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
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};
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "i82801db_smbus.h"
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#define SMBUS_IO_BASE 0x0f00
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static void enable_smbus(void)
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{
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device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
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print_spew("SMBus controller enabled\r\n");
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pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
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/* Set smbus enable */
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pci_write_config8(dev, 0x40, 1);
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/* Set smbus iospace enable */
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pci_write_config8(dev, 0x4, 1);
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/* SMBALERT_DIS */
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pci_write_config8(dev, 0x11, 4);
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/* Disable interrupt generation */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
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{
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if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
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return;
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}
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print_debug("Unimplemented smbus_write_byte() called.\r\n");
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#if 0
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/* setup transaction */
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/* disable interrupts */
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outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
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SMBUS_IO_BASE + SMBGCTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set up for a byte data write */ /* FIXME */
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outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
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/* clear the data word...*/
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outw(val, SMBUS_IO_BASE + SMBHSTDAT);
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/* start the command */
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outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
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/* poll for transaction completion */
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smbus_wait_until_done(SMBUS_IO_BASE);
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#endif
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return;
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}
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static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
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unsigned data1, unsigned data2)
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{
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unsigned char global_control_register;
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unsigned char global_status_register;
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unsigned char byte;
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unsigned char stat;
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int i;
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/* chear the PM timeout flags, SECOND_TO_STS */
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outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
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if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
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return -2;
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}
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/* setup transaction */
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/* Obtain ownership */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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for(stat=0;(stat&0x40)==0;) {
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stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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}
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/* clear the done bit */
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outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
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/* disable interrupts */
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outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
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/* set the command address */
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outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set the block length */
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outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
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/* try sending out the first byte of data here */
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byte=(data1>>(0))&0x0ff;
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outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
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/* issue a block write command */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
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SMBUS_IO_BASE + SMBHSTCTL);
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for(i=0;i<length;i++) {
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/* poll for transaction completion */
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if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
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|
||||||
return -3;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* load the next byte */
|
|
||||||
if(i>3)
|
|
||||||
byte=(data2>>(i%4))&0x0ff;
|
|
||||||
else
|
|
||||||
byte=(data1>>(i))&0x0ff;
|
|
||||||
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
|
|
||||||
|
|
||||||
/* clear the done bit */
|
|
||||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
|
|
||||||
SMBUS_IO_BASE + SMBHSTSTAT);
|
|
||||||
}
|
|
||||||
|
|
||||||
print_debug("SMBUS Block complete\r\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
Loading…
Reference in New Issue