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Removal of i82801DB (ICH4) 

There are no boards that use the i82801DB (ICH4). The code does NOT work.

Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith 2008-04-01 02:42:52 +00:00 committed by Ed Swierk
parent c4e052cd50
commit 868de9838c
6 changed files with 0 additions and 367 deletions
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11
src/southbridge/intel/i82801db/Config.lb
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@ -1,11 +0,0 @@
config chip.h
driver i82801db.o
driver i82801db_uhci.o
driver i82801db_lpc.o
driver i82801db_ide.o
driver i82801db_ehci.o
driver i82801db_smbus.o
driver i82801db_pci.o
driver i82801db_ac97.o
object i82801db_watchdog.o
object i82801db_reset.o

55
src/southbridge/intel/i82801db/chip.h
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@ -1,55 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef I82801DB_CHIP_H
#define I82801DB_CHIP_H
struct southbridge_intel_i82801db_config
{
#define ICH5R_GPIO_USE_MASK 0x03
#define ICH5R_GPIO_USE_DEFAULT 0x00
#define ICH5R_GPIO_USE_AS_NATIVE 0x01
#define ICH5R_GPIO_USE_AS_GPIO 0x02
#define ICH5R_GPIO_SEL_MASK 0x0c
#define ICH5R_GPIO_SEL_DEFAULT 0x00
#define ICH5R_GPIO_SEL_OUTPUT 0x04
#define ICH5R_GPIO_SEL_INPUT 0x08
#define ICH5R_GPIO_LVL_MASK 0x30
#define ICH5R_GPIO_LVL_DEFAULT 0x00
#define ICH5R_GPIO_LVL_LOW 0x10
#define ICH5R_GPIO_LVL_HIGH 0x20
#define ICH5R_GPIO_LVL_BLINK 0x30
#define ICH5R_GPIO_INV_MASK 0xc0
#define ICH5R_GPIO_INV_DEFAULT 0x00
#define ICH5R_GPIO_INV_OFF 0x40
#define ICH5R_GPIO_INV_ON 0x80
/* GPIO use select */
unsigned char gpio[64];
unsigned int pirq_a_d;
unsigned int pirq_e_h;
int enable_native_ide;
};
extern struct chip_operations southbridge_intel_i82801db_ops;
#endif /* I82801DB_CHIP_H */

34
src/southbridge/intel/i82801db/cmos_failover.c
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@ -1,34 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
//kind of cmos_err for ich5
#define RTC_FAILED (1 <<2)
#define GEN_PMCON_3 0xa4
static void check_cmos_failed(void)
{
uint8_t byte;
byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
if( byte & RTC_FAILED){
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}

64
src/southbridge/intel/i82801db/i82801db.c
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@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801db.h"
void i82801db_enable(device_t dev)
{
device_t lpc_dev;
uint16_t word;
printk_debug("Entering %s\n", __FUNCTION__);
/* See if we are behind the i82801db pci bridge
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
*/
lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
if (!lpc_dev) {
return;
}
word = 0x0040;
pci_write_config16(lpc_dev, 0xf2, word);
/*
if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
index = dev->path.u.pci.devfn & 7;
}
else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
index = (dev->path.u.pci.devfn & 7) +8;
}
reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
reg &= ~(1 << index);
if (!dev->enabled) {
reg |= (1 << index);
}
if (reg != reg_old) {
printk_debug("Trying to enable device, [0:1f:0] reg 0xf2 <- %04x\n", reg);
pci_write_config16(lpc_dev, 0xf2, reg);
}
*/
}
struct chip_operations southbridge_intel_i82801db_ops = {
CHIP_NAME("Intel 82801DB Southbridge")
.enable_dev = i82801db_enable,
};

55
src/southbridge/intel/i82801db/i82801db_ac97.c
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@ -1,55 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "i82801db.h"
static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* Write the subsystem vendor and device id */
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = ac97_set_subsystem,
};
static struct device_operations ac97_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.enable = i82801db_enable,
.ops_pci = &lops_pci,
};
static const struct pci_driver ac97_audio_driver __pci_driver = {
.ops = &ac97_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
};
static const struct pci_driver ac97_modem_driver __pci_driver = {
.ops = &ac97_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
};

148
src/southbridge/intel/i82801db/i82801db_early_smbus.c
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@ -1,148 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "i82801db_smbus.h"
#define SMBUS_IO_BASE 0x0f00
static void enable_smbus(void)
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
print_spew("SMBus controller enabled\r\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
/* Set smbus enable */
pci_write_config8(dev, 0x40, 1);
/* Set smbus iospace enable */
pci_write_config8(dev, 0x4, 1);
/* SMBALERT_DIS */
pci_write_config8(dev, 0x11, 4);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
static int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
return;
}
print_debug("Unimplemented smbus_write_byte() called.\r\n");
#if 0
/* setup transaction */
/* disable interrupts */
outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
SMBUS_IO_BASE + SMBGCTL);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data write */ /* FIXME */
outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
/* clear any lingering errors, so the transaction will run */
/* Do I need to write the bits to a 1 to clear an error? */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
/* clear the data word...*/
outw(val, SMBUS_IO_BASE + SMBHSTDAT);
/* start the command */
outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
/* poll for transaction completion */
smbus_wait_until_done(SMBUS_IO_BASE);
#endif
return;
}
static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
unsigned data1, unsigned data2)
{
unsigned char global_control_register;
unsigned char global_status_register;
unsigned char byte;
unsigned char stat;
int i;
/* chear the PM timeout flags, SECOND_TO_STS */
outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
return -2;
}
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
for(stat=0;(stat&0x40)==0;) {
stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
/* clear the done bit */
outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
/* set the device I'm talking too */
outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
/* set the command address */
outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set the block length */
outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
/* try sending out the first byte of data here */
byte=(data1>>(0))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
/* issue a block write command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
for(i=0;i<length;i++) {
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
return -3;
}
/* load the next byte */
if(i>3)
byte=(data2>>(i%4))&0x0ff;
else
byte=(data1>>(i))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
/* clear the done bit */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
SMBUS_IO_BASE + SMBHSTSTAT);
}
print_debug("SMBUS Block complete\r\n");
return 0;
}