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Revert "mb/pcengines/apu2: add reset logic for PCIe slots" 

This reverts commit c04871a398.

Reason for revert: Many apu2 users reported issues with PCIe modules
detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught
by 3mdeb validation stands and hardware configuration.

Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2020-04-04 08:49:21 +00:00
parent 7daf3cd32e
commit 869ac71483
3 changed files with 5 additions and 95 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
src/mainboard/pcengines/apu2/BiosCallOuts.c
View File

@ -2,7 +2,6 @@
/* This file is part of the coreboot project. */
#include <AGESA.h>
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <spd_bin.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
@ -14,7 +13,6 @@
#include "hudson.h"
static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPciExSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
@ -23,7 +21,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_GNB_PCIE_SLOT_RESET, board_GnbPciExSlotReset },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }
};
@ -131,71 +128,3 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
return AGESA_SUCCESS;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPciExSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
PCIe_SLOT_RESET_INFO *ResetInfo;
uint32_t GpioData;
uint8_t GpioValue;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
switch (ResetInfo->ResetId) {
/*
* ResetID 1 = PCIE_RST# affects all PCIe slots on all boards except
* apu2. ResetID 1 does not need any GPIO.
*/
case 1:
Status = AGESA_SUCCESS;
break;
case 51: /* GPIO51 resets mPCIe1 slot on apu2 */
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
GpioData = gpio1_read32(0x8);
printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n",
__func__, ResetInfo->ResetId, GpioData);
GpioValue = gpio1_read8(0xa);
GpioValue &= ~BIT6;
gpio1_write8(0xa, GpioValue);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
GpioData = gpio1_read32(0x8);
printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n",
__func__, ResetInfo->ResetId, GpioData);
GpioValue = gpio1_read8(0xa);
GpioValue |= BIT6;
gpio1_write8(0xa, GpioValue);
Status = AGESA_SUCCESS;
break;
}
break;
case 55: /* GPIO51 resets mPCIe2 slot on apu2 */
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
GpioData = gpio1_read32(0xc);
printk(BIOS_DEBUG, "%s: ResetID %u assert %08x\n",
__func__, ResetInfo->ResetId, GpioData);
GpioValue = gpio1_read8(0xe);
GpioValue &= ~BIT6;
gpio1_write8(0xa, GpioValue);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
GpioData = gpio1_read32(0xc);
printk(BIOS_DEBUG, "%s: ResetID %u deassert %08x\n",
__func__, ResetInfo->ResetId, GpioData);
GpioValue = gpio1_read8(0xe);
GpioValue |= BIT6;
gpio1_write8(0xa, GpioValue);
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
}

20
src/mainboard/pcengines/apu2/OemCustomize.c
View File

@ -4,16 +4,6 @@
#include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h>
#define PCIE_NIC_RESET_ID 1
#if CONFIG(BOARD_PCENGINES_APU2)
#define PCIE_GFX_RESET_ID 55
#define PCIE_PORT3_RESET_ID 51
#else
#define PCIE_GFX_RESET_ID PCIE_NIC_RESET_ID
#define PCIE_PORT3_RESET_ID PCIE_NIC_RESET_ID
#endif
static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
@ -23,7 +13,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1,
PCIE_PORT3_RESET_ID,
0x01,
0)
},
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
@ -35,7 +25,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1,
PCIE_NIC_RESET_ID,
0x02,
0)
},
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
@ -47,7 +37,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1,
PCIE_NIC_RESET_ID,
0x03,
0)
},
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
@ -59,7 +49,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1,
PCIE_NIC_RESET_ID,
0x04,
0)
},
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
@ -71,7 +61,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmL0sL1,
PCIE_GFX_RESET_ID,
0x05,
0)
}
};

9
src/mainboard/pcengines/apu2/romstage.c
View File

@ -27,15 +27,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
/* Release GPIO32/33 for other uses. */
pm_write8(0xea, 1);
/*
* Assert resets on the PCIe slots, since AGESA calls deassert callout
* only. Only apu2 uses GPIOs to reset PCIe slots.
*/
if (CONFIG(BOARD_PCENGINES_APU2)) {
gpio1_write8(0xa, gpio1_read8(0xa) & ~(1 << 6));
gpio1_write8(0xe, gpio1_read8(0xe) & ~(1 << 6));
}
}
static void early_lpc_init(void)