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ec/lenovo/pmh7: support 9bit address space 

The pmh7 has at least a 9bit address space.
The h8s allows to access the 9th address space by using io port
0x15ed as second address register.

The pmh7 is connected via SPI to the h8s. The h8s is acting as
proxy to access the address space.

Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
This commit is contained in:
Alexander Couzens 2018-08-17 18:47:52 +02:00 committed by Felix Held
parent df5e6f64b6
commit 86b8d176e8
2 changed files with 6 additions and 3 deletions
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6
src/ec/lenovo/pmh7/pmh7.c
View File

@ -103,13 +103,15 @@ void pmh7_register_clear_bit(int reg, int bit)
char pmh7_register_read(int reg) char pmh7_register_read(int reg)
{ {
outb(reg, EC_LENOVO_PMH7_ADDR); outb(reg & 0xff, EC_LENOVO_PMH7_ADDR_L);
outb((reg & 0xff00) >> 8, EC_LENOVO_PMH7_ADDR_H);
return inb(EC_LENOVO_PMH7_DATA); return inb(EC_LENOVO_PMH7_DATA);
} }
void pmh7_register_write(int reg, int val) void pmh7_register_write(int reg, int val)
{ {
outb(reg, EC_LENOVO_PMH7_ADDR); outb(reg & 0xff, EC_LENOVO_PMH7_ADDR_L);
outb((reg & 0xff00) >> 8, EC_LENOVO_PMH7_ADDR_H);
outb(val, EC_LENOVO_PMH7_DATA); outb(val, EC_LENOVO_PMH7_DATA);
} }

3
src/ec/lenovo/pmh7/pmh7.h
View File

@ -19,7 +19,8 @@
#define EC_LENOVO_PMH7_INDEX 0x77 #define EC_LENOVO_PMH7_INDEX 0x77
#define EC_LENOVO_PMH7_BASE 0x15e0 #define EC_LENOVO_PMH7_BASE 0x15e0
#define EC_LENOVO_PMH7_ADDR (EC_LENOVO_PMH7_BASE + 0x0c) #define EC_LENOVO_PMH7_ADDR_L (EC_LENOVO_PMH7_BASE + 0x0c)
#define EC_LENOVO_PMH7_ADDR_H (EC_LENOVO_PMH7_BASE + 0x0d)
#define EC_LENOVO_PMH7_DATA (EC_LENOVO_PMH7_BASE + 0x0e) #define EC_LENOVO_PMH7_DATA (EC_LENOVO_PMH7_BASE + 0x0e)
#define EC_LENOVO_PMH7_REG_ID 0xc2 #define EC_LENOVO_PMH7_REG_ID 0xc2