Coding-style and whitespace fixes (also to make the code more similar
the Lippert Cool SpaceRunner LX which is already in svn). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
f31ca16793
commit
86c9b88392
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@ -3,8 +3,6 @@
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##
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## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
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##
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## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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@ -20,15 +18,17 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
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##
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## Compute the location and size of where this firmware image
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## (coreboot plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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@ -38,12 +38,12 @@ end
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##
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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##
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## Compute where this copy of coreboot will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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##
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## Compute a range of ROM that can cached to speed up coreboot,
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@ -52,8 +52,8 @@ default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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default XIP_ROM_SIZE = 64 * 1024
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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##
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@ -73,7 +73,7 @@ if HAVE_PIRQ_TABLE
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end
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if USE_DCACHE_RAM
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#compile cache_as_ram.c to auto.inc
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# compile cache_as_ram.c to auto.inc
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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@ -136,21 +136,24 @@ if USE_DCACHE_RAM
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end
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##
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## Include the secondary Configuration files
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## Include the secondary configuration files
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##
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dir /pc80
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config chip.h
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register "sio_gp1x_config" = "0x20" # bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED
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# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED.
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register "sio_gp1x_config" = "0x20"
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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device pci 1.2 on end # AES
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
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chip southbridge/amd/cs5536 # Southbridge
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# IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power...
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
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# UARTs, etc IRQs. OK
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register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
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register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
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register "lpc_serirq_mode" = "1"
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@ -171,7 +174,7 @@ chip northbridge/amd/lx
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device pci b.0 on end # Slot1
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device pci c.0 on end # IT8888
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device pci e.0 on end # Ethernet
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device pci f.0 on # ISA Bridge
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device pci f.0 on # ISA bridge
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chip superio/ite/it8712f
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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@ -186,7 +189,7 @@ chip northbridge/amd/lx
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel Port
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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@ -195,29 +198,29 @@ chip northbridge/amd/lx
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # Keyboard
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device pnp 2e.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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device pnp 2e.6 on # PS/2 mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO
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io 0x62 = 0x1220
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#io 0x64 = 0x1200
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# io 0x64 = 0x1200
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.9 off # GAME
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device pnp 2e.9 off # Game port
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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end
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end
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device pci f.2 on end # IDE Controller
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device pci f.2 on end # IDE controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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@ -3,8 +3,6 @@
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##
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## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
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##
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## Based on Options.lb from AMD's DB800 mainboard.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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@ -20,6 +18,8 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## Based on Options.lb from AMD's DB800 mainboard.
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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@ -80,71 +80,71 @@ uses DCACHE_RAM_SIZE
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uses PIRQ_ROUTE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 512*1024
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default ROM_SIZE = 512 * 1024
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###
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### Build options
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###
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default CONFIG_CONSOLE_VGA=0
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default CONFIG_VIDEO_MB=8
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default CONFIG_PCI_ROM_RUN=0
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default CONFIG_CONSOLE_VGA = 0
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default CONFIG_VIDEO_MB = 8
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default CONFIG_PCI_ROM_RUN = 0
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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default HAVE_FALLBACK_BOOT = 1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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default HAVE_MP_TABLE = 0
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##
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## Build code to reset the motherboard from coreboot
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##
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default HAVE_HARD_RESET=0
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default HAVE_HARD_RESET = 0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=7
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default PIRQ_ROUTE=1
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 7
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default PIRQ_ROUTE = 1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=0
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default HAVE_OPTION_TABLE = 0
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###
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### coreboot layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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default ROM_IMAGE_SIZE = 64 * 1024
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default FALLBACK_SIZE = 128 * 1024
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xc8000
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default DCACHE_RAM_SIZE=0x08000
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default USE_DCACHE_RAM = 1
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default DCACHE_RAM_BASE = 0xc8000
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default DCACHE_RAM_SIZE = 0x08000
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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default STACK_SIZE = 8 * 1024
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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default HEAP_SIZE = 16 * 1024
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##
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## Only use the option table in a normal image
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@ -159,36 +159,36 @@ default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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default CROSS_COMPILE = ""
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default CC = "$(CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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default CONFIG_CONSOLE_SERIAL8250 = 1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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default TTYS0_BAUD = 115200
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#default TTYS0_BAUD = 57600
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#default TTYS0_BAUD = 38400
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#default TTYS0_BAUD = 19200
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#default TTYS0_BAUD = 9600
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#default TTYS0_BAUD = 4800
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#default TTYS0_BAUD = 2400
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#default TTYS0_BAUD = 1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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default TTYS0_BASE = 0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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default TTYS0_LCS = 0x3
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# Compile extra debugging code
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default DEBUG=1
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default DEBUG = 1
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##
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### Select the coreboot loglevel
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@ -204,8 +204,8 @@ default DEBUG=1
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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default DEFAULT_CONSOLE_LOGLEVEL = 8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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default MAXIMUM_CONSOLE_LOGLEVEL = 8
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end
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@ -4,8 +4,6 @@
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* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
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@ -21,6 +19,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */
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#define ASSEMBLY 1
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#include <stdlib.h>
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@ -52,7 +52,9 @@
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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if (device != DIMM0) return 0xFF; // no DIMM1, don't even try
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if (device != DIMM0)
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return 0xFF; /* No DIMM1, don't even try. */
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return smbus_read_byte(device, address);
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}
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@ -120,11 +122,12 @@ static void mb_gpio_init(void)
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{
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int i;
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/* Init SuperIO WDT, GPIOs. Done early, WDT init may trigger reset! */
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/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
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it8712f_enter_conf();
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for (i=0; i<ARRAY_SIZE(sio_init_table); i++) {
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for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
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u16 val = sio_init_table[i];
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outb((u8)val, SIO_INDEX); outb(val>>8, SIO_DATA);
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outb((u8)val, SIO_INDEX);
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outb(val >> 8, SIO_DATA);
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}
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it8712f_exit_conf();
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}
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@ -142,10 +145,11 @@ void cache_as_ram_main(void)
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cs5536_early_setup();
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/* Note: must do this AFTER the early_setup! It is counting on some
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/*
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* Note: must do this AFTER the early_setup! It is counting on some
|
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* early MSR setup for CS5536.
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*/
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it8712f_enable_serial(0, TTYS0_BASE); // does not use its 1st parameter
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it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter
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mb_gpio_init();
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uart_init();
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console_init();
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|
|
|
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|
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@ -3,8 +3,6 @@
|
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*
|
||||
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* Based on chip.h from AMD's DB800 mainboard.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
|
|
@ -20,10 +18,13 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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/* Based on chip.h from AMD's DB800 mainboard. */
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|
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#include <stdint.h>
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|
||||
extern struct chip_operations mainboard_lippert_roadrunner_lx_ops;
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struct mainboard_lippert_roadrunner_lx_config {
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u8 sio_gp1x_config; // bit5=Live LED, bit2=RS485_EN2, bit1=RS485_EN1
|
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/* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */
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u8 sio_gp1x_config;
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};
|
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|
|
|
|||
|
|
@ -3,8 +3,6 @@
|
|||
*
|
||||
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* Based on irq_tables.c from AMD's DB800 mainboard.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
|
|
@ -20,6 +18,8 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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||||
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||||
/* Based on irq_tables.c from AMD's DB800 mainboard. */
|
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|
||||
#include <arch/pirq_routing.h>
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#include <console/console.h>
|
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#include <arch/io.h>
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|
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@ -47,7 +47,7 @@
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const struct irq_routing_table intel_irq_routing_table = {
|
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PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
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32 + 16 * IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */
|
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32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */
|
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
|
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|
|
@ -55,11 +55,11 @@ const struct irq_routing_table intel_irq_routing_table = {
|
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0x002B, /* Device */
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0, /* Crap (miniport) */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0xE0, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
|
||||
{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
|
||||
{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */
|
||||
|
|
|
|||
|
|
@ -3,8 +3,6 @@
|
|||
*
|
||||
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* Based on mainboard.c from AMD's DB800 mainboard.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
|
|
@ -20,6 +18,8 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Based on mainboard.c from AMD's DB800 mainboard. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
|
|
@ -29,13 +29,13 @@
|
|||
#include <device/pci_ids.h>
|
||||
#include "chip.h"
|
||||
|
||||
static const u16 ec_init_table[] = { // hi=data, lo=index
|
||||
0x1900, // enable monitoring
|
||||
0x0351, // TMPIN1,2 diode mode, TMPIN3 off
|
||||
0x805C, // unlock zero adjust
|
||||
0x7056, 0x3C57, // zero adjust TMPIN1,2
|
||||
0x005C, // lock zero adjust
|
||||
0xD014 // also set FAN_CTL polarity to Active High
|
||||
static const u16 ec_init_table[] = { /* hi=data, lo=index */
|
||||
0x1900, /* Enable monitoring */
|
||||
0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
|
||||
0x805C, /* Unlock zero adjust */
|
||||
0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
|
||||
0x005C, /* Lock zero adjust */
|
||||
0xD014 /* Also set FAN_CTL polarity to Active High */
|
||||
};
|
||||
|
||||
static void init(struct device *dev)
|
||||
|
|
@ -44,22 +44,24 @@ static void init(struct device *dev)
|
|||
unsigned int gpio_base, i;
|
||||
printk_debug("LiPPERT RoadRunner-LX ENTER %s\n", __FUNCTION__);
|
||||
|
||||
/* Init CS5536 GPIOs */
|
||||
gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0),
|
||||
PCI_BASE_ADDRESS_1) - 1;
|
||||
/* Init CS5536 GPIOs. */
|
||||
gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
|
||||
|
||||
outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
|
||||
outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
|
||||
outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
|
||||
outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
|
||||
outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED
|
||||
|
||||
/* Init Environment Controller */
|
||||
for (i=0; i<ARRAY_SIZE(ec_init_table); i++) {
|
||||
/* Init Environment Controller. */
|
||||
for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
|
||||
u16 val = ec_init_table[i];
|
||||
outb((u8)val, 0x0295); outb(val>>8, 0x0296);
|
||||
outb((u8)val, 0x0295);
|
||||
outb(val >> 8, 0x0296);
|
||||
}
|
||||
|
||||
outb(mb->sio_gp1x_config, 0x1220); // Simple-I/O GP17-10
|
||||
outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */
|
||||
printk_debug("LiPPERT RoadRunner-LX EXIT %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,24 +25,24 @@ target roadrunner-lx
|
|||
mainboard lippert/roadrunner-lx
|
||||
|
||||
# HACK to get the right TSC support.
|
||||
option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
|
||||
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
|
||||
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
|
||||
option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
|
||||
option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
|
||||
|
||||
## Load payload (e.g. Linux) from IDE.
|
||||
#option CONFIG_ROM_PAYLOAD=0
|
||||
#option CONFIG_IDE=1
|
||||
#option CONFIG_FS_PAYLOAD=1
|
||||
#option CONFIG_FS_EXT2=1
|
||||
#option AUTOBOOT_DELAY=0
|
||||
#option AUTOBOOT_CMDLINE="hda1:/payload.elf"
|
||||
#option CONFIG_ROM_PAYLOAD = 0
|
||||
#option CONFIG_IDE = 1
|
||||
#option CONFIG_FS_PAYLOAD = 1
|
||||
#option CONFIG_FS_EXT2 = 1
|
||||
#option AUTOBOOT_DELAY = 0
|
||||
#option AUTOBOOT_CMDLINE = "hda1:/payload.elf"
|
||||
|
||||
# Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash,
|
||||
# however it can be replaced with a 1 MB chip.
|
||||
option ROM_SIZE=512*1024-36*1024
|
||||
#option ROM_SIZE=1024*1024-36*1024
|
||||
option FALLBACK_SIZE=ROM_SIZE
|
||||
option ROM_SIZE = (512 * 1024) - (36 * 1024)
|
||||
#option ROM_SIZE = (1024 * 1024) - (36 * 1024)
|
||||
option FALLBACK_SIZE = ROM_SIZE
|
||||
|
||||
#option DEFAULT_CONSOLE_LOGLEVEL = 4
|
||||
#option MAXIMUM_CONSOLE_LOGLEVEL = 4
|
||||
|
|
@ -51,12 +51,12 @@ option FALLBACK_SIZE=ROM_SIZE
|
|||
option CONFIG_COMPRESS = 1
|
||||
|
||||
romimage "image"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=64*1024
|
||||
option COREBOOT_EXTRA_VERSION=".0"
|
||||
option USE_FALLBACK_IMAGE = 1
|
||||
option ROM_IMAGE_SIZE = 64 * 1024
|
||||
option COREBOOT_EXTRA_VERSION = ".0"
|
||||
payload ../payload.elf
|
||||
# If getting payload from IDE
|
||||
#payload /dev/null
|
||||
# payload /dev/null
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom ROM_SIZE "image"
|
||||
|
|
|
|||
Loading…
Reference in New Issue