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mb/google/drallion: Disable GBE in firmware for drallion variants 

BUG: None
TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>
Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Thejaswani Putta 2019-09-20 15:13:22 -07:00 committed by Patrick Georgi
parent 459f493486
commit 86cb421df6
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
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@ -417,6 +417,6 @@ chip soc/intel/cannonlake
device pci 1f.3 on end # Intel HDA device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI device pci 1f.5 on end # PCH SPI
device pci 1f.6 on end # GbE device pci 1f.6 off end # GbE
end end
end end