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mb/google/var/taeko: Add gpios to lock 

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taeko boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib30815dbe99342b6afd9af9f1aa9ff61c9a4fe80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-08 11:28:48 +08:00 committed by Felix Held
parent b1963920b3
commit 86ce03361b
1 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/mainboard/google/brya/variants/taeko/gpio.c
View File

@ -33,9 +33,9 @@ static const struct pad_config override_gpio_table[] = {
/* B2 : VRALERT# ==> NC */ /* B2 : VRALERT# ==> NC */
PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B2, NONE),
/* B3 : PROC_GP2 ==> NC */ /* B3 : PROC_GP2 ==> NC */
PAD_NC(GPP_B3, NONE), PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
/* B15 : TIME_SYNC0 ==> NC */ /* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE), PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* C3 : SML0CLK ==> NC */ /* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE), PAD_NC(GPP_C3, NONE),
@ -45,23 +45,23 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_C6, NONE), PAD_NC(GPP_C6, NONE),
/* D3 : ISH_GP3 ==> NC */ /* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE), PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D9 : ISH_SPI_CS# ==> NC */ /* D9 : ISH_SPI_CS# ==> NC */
PAD_NC(GPP_D9, NONE), PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
/* D10 : ISH_SPI_CLK ==> NC */ /* D10 : ISH_SPI_CLK ==> NC */
PAD_NC(GPP_D10, NONE), PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
/* D13 : ISH_UART0_RXD ==> NC */ /* D13 : ISH_UART0_RXD ==> NC */
PAD_NC(GPP_D13, NONE), PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> NC */ /* D14 : ISH_UART0_TXD ==> NC */
PAD_NC(GPP_D14, NONE), PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
/* D15 : ISH_UART0_RTS# ==> NC */ /* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC(GPP_D15, NONE), PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> NC */ /* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC(GPP_D16, NONE), PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* D17 : UART1_RXD ==> NC */ /* D17 : UART1_RXD ==> NC */
PAD_NC(GPP_D17, NONE), PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
/* E0 : SATAXPCIE0 ==> NC */ /* E0 : SATAXPCIE0 ==> NC */
PAD_NC(GPP_E0, NONE), PAD_NC(GPP_E0, NONE),
@ -70,11 +70,11 @@ static const struct pad_config override_gpio_table[] = {
/* E5 : SATA_DEVSLP1 ==> NC */ /* E5 : SATA_DEVSLP1 ==> NC */
PAD_NC(GPP_E5, NONE), PAD_NC(GPP_E5, NONE),
/* E10 : THC0_SPI1_CS# ==> NC */ /* E10 : THC0_SPI1_CS# ==> NC */
PAD_NC(GPP_E10, NONE), PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
/* E16 : RSVD_TP ==> NC */ /* E16 : RSVD_TP ==> NC */
PAD_NC(GPP_E16, NONE), PAD_NC(GPP_E16, NONE),
/* E17 : THC0_SPI1_INT# ==> NC */ /* E17 : THC0_SPI1_INT# ==> NC */
PAD_NC(GPP_E17, NONE), PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : DDP1_CTRLCLK ==> NC */ /* E18 : DDP1_CTRLCLK ==> NC */
PAD_NC(GPP_E18, NONE), PAD_NC(GPP_E18, NONE),
/* E19 : DDP1_CTRLDATA ==> NC */ /* E19 : DDP1_CTRLDATA ==> NC */
@ -106,7 +106,7 @@ static const struct pad_config override_gpio_table[] = {
/* H9 : I2C4_SCL ==> NC */ /* H9 : I2C4_SCL ==> NC */
PAD_NC(GPP_H9, NONE), PAD_NC(GPP_H9, NONE),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, DEEP), PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
/* H15 : DDPB_CTRLCLK ==> NC */ /* H15 : DDPB_CTRLCLK ==> NC */
PAD_NC(GPP_H15, NONE), PAD_NC(GPP_H15, NONE),
/* H17 : DDPB_CTRLDATA ==> NC */ /* H17 : DDPB_CTRLDATA ==> NC */