skylake: ACPI: Move storage controllers to separate file
Move the storage controller devices out of serialio.asl and into a new scs.asl file and implement the power gating workarounds for D0 and D3 transitions. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529 Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295908 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
9171f1ab8d
commit
86f23acee5
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@ -46,6 +46,8 @@
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/* SMBus 0:1f.3 */
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/* SMBus 0:1f.3 */
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#include "smbus.asl"
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#include "smbus.asl"
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/* Storage Controllers */
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#include "scs.asl"
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/* USB XHCI 0:14.0 */
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/* USB XHCI 0:14.0 */
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#include "xhci.asl"
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#include "xhci.asl"
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@ -0,0 +1,125 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* Intel Storage Controllers */
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Device (EMMC)
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{
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Name (_ADR, 0x001E0004)
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Name (_DDN, "eMMC Controller")
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OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
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Field (EMCR, DWordAcc, NoLock, Preserve)
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{
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Offset (0x84), /* PMECTRLSTATUS */
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D0D3, 2, /* POWERSTATE */
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Offset (0xa2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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Method (_PS0, 0, Serialized)
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{
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/* Disable Power Good */
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Store (0, ^PGEN)
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/* Clear bits 31, 6, 2, 0 */
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^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
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Sleep (2)
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/* Set bits 31, 6, 2, 0 */
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^^PCRO (PID_SCS, 0x600, 0x80000045)
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/* Set Power State to D0 */
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Store (0, ^D0D3)
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Store (^D0D3, Local0)
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}
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Method (_PS3, 0, Serialized)
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{
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/* Enable Power Good */
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Store (1, ^PGEN)
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/* Set Power State to D0 */
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Store (3, ^D0D3)
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Store (^D0D3, Local0)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (0)
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}
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}
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}
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Device (SDXC)
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{
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Name (_ADR, 0x001E0006)
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Name (_DDN, "SD Controller")
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OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
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Field (SDCR, DWordAcc, NoLock, Preserve)
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{
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Offset (0x84), /* PMECTRLSTATUS */
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D0D3, 2, /* POWERSTATE */
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Offset (0xa2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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Method (_PS0, 0, Serialized)
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{
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/* Disable Power Good */
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Store (0, ^PGEN)
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/* Clear bits 8, 7, 2, 0 */
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^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
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Sleep (2)
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/* Set bits 31, 6, 2, 0 */
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^^PCRO (PID_SCS, 0x600, 0x00000185)
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/* Set Power State to D0 */
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Store (0, ^D0D3)
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Store (^D0D3, Local0)
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}
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Method (_PS3, 0, Serialized)
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{
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/* Enable Power Good */
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Store (1, ^PGEN)
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/* Set Power State to D0 */
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Store (3, ^D0D3)
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Store (^D0D3, Local0)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (1)
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}
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}
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}
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@ -618,32 +618,3 @@ Device (UAR2)
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^^LPD3 (\SAB1, \SAEN)
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^^LPD3 (\SAB1, \SAEN)
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}
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}
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}
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}
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Device (PEMC)
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{
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Name (_ADR, 0x001E0004)
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0x0, NotSerialized)
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{
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Return (0)
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}
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}
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}
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/* SD controller */
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Device (PSDC)
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{
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Name (_ADR, 0x001E0006)
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0x0, NotSerialized)
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{
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Return (1)
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}
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}
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}
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