cpu/amd/model_10xxx: Add support for early cbmem

mainboards/amd/fam10: Initialize cbmem area after raminit

When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE
When GFXUMA is disabled, CBMEM is placed at TOM
This matches the behaviour present before conversion to early
CBMEM.

The CBMEM location code implicitly assumes TOM does not change
between romstage and ramstage.  TOM is set by romstage raminit,
and is never changed by romstage or ramstage afterward.  As
the CBMEM location is positioned at a specific offset from TOM
that is known to both romstage and ramstage early CBMEM is safe
on Fam10h systems.

TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp
tables from romstage and cbmem log tables from ramstage.

Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8489
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>

src/cpu/amd/model_10xxx/ram_calc.c

@@ -22,6 +22,8 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 
+#include <cbmem.h>
+
 #include "ram_calc.h"
 
 uint64_t get_uma_memory_size(uint64_t topmem)
@@ -41,3 +43,10 @@ uint64_t get_uma_memory_size(uint64_t topmem)
 
 	return uma_size;
 }
+
+void *cbmem_top(void)
+{
+	uint32_t topmem = rdmsr(TOP_MEM).lo;
+
+	return (void *) topmem - get_uma_memory_size(topmem);
+}

src/mainboard/advansus/a785e-i/romstage.c

@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/amd/bimini_fam10/romstage.c

@@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/asus/kfsn4-dre/romstage.c

@@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 	printk(BIOS_DEBUG, "disable_spd()\n");

src/mainboard/asus/m4a78-em/romstage.c

@@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/asus/m4a785-m/romstage.c

@@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/asus/m5a88-v/romstage.c

@@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/avalue/eax-785e/romstage.c

@@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 	bcm5785_early_setup();

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/jetway/pa78vm5/romstage.c

@@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 	post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -292,6 +292,7 @@ post_code(0x40);
 
  printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
+ cbmem_initialize_empty();
  post_code(0x41);
 
  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 /*

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
 	post_code(0x41);
 
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.

src/northbridge/amd/amdfam10/Kconfig

@@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10
 	select HYPERTRANSPORT_PLUGIN_SUPPORT
 	select MMCONF_SUPPORT
 	select PER_DEVICE_ACPI_TABLES
-	select LATE_CBMEM_INIT
 
 if NORTHBRIDGE_AMD_AMDFAM10
 config AGP_APERTURE_SIZE

src/northbridge/amd/amdfam10/northbridge.c

@@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev)
 	}
 
 #if CONFIG_GFXUMA
-	set_top_of_ram(uma_memory_base);
 	uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
-#else
-	set_top_of_ram(bsp_topmem());
 #endif
 
 	for(link = dev->link_list; link; link = link->next) {