cpu: Get rid of CPU_SPECIFIC_OPTIONS

Remove dummy CPU_SPECIFIC_OPTIONS.

Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76681
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2023-07-21 07:38:54 +02:00
parent 33201ab49f
commit 86f4f2fb34
11 changed files with 21 additions and 54 deletions

View File

@ -1,11 +1,6 @@
config CPU_INTEL_HASWELL
bool
if CPU_INTEL_HASWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select SSE2
select UDELAY_TSC
@ -19,6 +14,8 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_ASAN_IN_ROMSTAGE
select CPU_INTEL_COMMON_VOLTAGE
if CPU_INTEL_HASWELL
config SMM_TSEG_SIZE
hex
default 0x800000

View File

@ -1,10 +1,5 @@
config CPU_INTEL_MODEL_2065X
bool
if CPU_INTEL_MODEL_2065X
config CPU_SPECIFIC_OPTIONS
def_bool y
select HAVE_EXP_X86_64_SUPPORT
select ARCH_X86
select SSE2
@ -16,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
if CPU_INTEL_MODEL_2065X
config SMM_TSEG_SIZE
hex
default 0x800000

View File

@ -1,10 +1,5 @@
config CPU_INTEL_MODEL_206AX
bool
if CPU_INTEL_MODEL_206AX
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT
select SSE2
@ -16,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
if CPU_INTEL_MODEL_206AX
config SMM_TSEG_SIZE
hex
default 0x800000

View File

@ -2,11 +2,6 @@
config CPU_INTEL_SLOT_1
bool
if CPU_INTEL_SLOT_1
config SLOT_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_65X
select CPU_INTEL_MODEL_67X
select CPU_INTEL_MODEL_68X
@ -19,6 +14,8 @@ config SLOT_SPECIFIC_OPTIONS
select SETUP_XIP_CACHE
select RESERVE_MTRRS_FOR_OS
if CPU_INTEL_SLOT_1
config DCACHE_RAM_BASE
hex
default 0xfefc0000

View File

@ -1,13 +1,10 @@
config CPU_INTEL_SOCKET_441
bool
if CPU_INTEL_SOCKET_441
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_106CX
select SETUP_XIP_CACHE
if CPU_INTEL_SOCKET_441
config DCACHE_RAM_BASE
hex
default 0xfefc0000

View File

@ -1,12 +1,9 @@
config CPU_INTEL_SOCKET_BGA956
bool
select CPU_INTEL_MODEL_1067X
if CPU_INTEL_SOCKET_BGA956
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_1067X
config DCACHE_RAM_BASE
hex
default 0xfefc0000

View File

@ -1,15 +1,12 @@
config CPU_INTEL_SOCKET_FCBGA559
bool
select CPU_INTEL_MODEL_106CX
select CPU_HAS_L2_ENABLE_MSR
help
Select this socket on Intel Pineview
if CPU_INTEL_SOCKET_FCBGA559
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_106CX
select CPU_HAS_L2_ENABLE_MSR
config DCACHE_RAM_BASE
hex
default 0xfefc0000

View File

@ -1,16 +1,13 @@
config CPU_INTEL_SOCKET_LGA775
bool
if CPU_INTEL_SOCKET_LGA775
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_6FX
select CPU_INTEL_MODEL_F3X
select CPU_INTEL_MODEL_F4X
select CPU_INTEL_MODEL_1067X
select SIPI_VECTOR_IN_ROM
if CPU_INTEL_SOCKET_LGA775
config DCACHE_RAM_SIZE
hex
default 0x8000 # 32 kB

View File

@ -1,13 +1,10 @@
config CPU_INTEL_SOCKET_M
bool
if CPU_INTEL_SOCKET_M
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_6EX
select CPU_INTEL_MODEL_6FX
if CPU_INTEL_SOCKET_M
config DCACHE_RAM_BASE
hex
default 0xfefc0000

View File

@ -1,10 +1,5 @@
config CPU_INTEL_SOCKET_MPGA604
bool
if CPU_INTEL_SOCKET_MPGA604
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_F2X
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
@ -12,6 +7,8 @@ config SOCKET_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
if CPU_INTEL_SOCKET_MPGA604
config DCACHE_RAM_BASE
hex
default 0xfefc0000

View File

@ -1,13 +1,10 @@
config CPU_INTEL_SOCKET_P
bool
if CPU_INTEL_SOCKET_P
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_MODEL_1067X
select CPU_INTEL_MODEL_6FX
if CPU_INTEL_SOCKET_P
config DCACHE_RAM_BASE
hex
default 0xfefc0000