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Fix MMCONF_SUPPORT_DEFAULT for ramstage 

Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.

The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.

Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-07-03 09:44:28 +03:00 committed by Stefan Reinauer
parent 20b6d91fd3
commit 872c922296
12 changed files with 21 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/x86/include/arch/pci_ops.h
View File

@ -7,9 +7,19 @@ extern const struct pci_bus_operations pci_cf8_conf1;
extern const struct pci_bus_operations pci_ops_mmconf;
#endif
#if CONFIG_MMCONF_SUPPORT_DEFAULT
#define pci_bus_default_ops &pci_ops_mmconf
#else
#define pci_bus_default_ops &pci_cf8_conf1
#endif
static inline const struct pci_bus_operations *pci_config_default(void)
{
#if CONFIG_MMCONF_SUPPORT_DEFAULT
return &pci_ops_mmconf;
#else
return &pci_cf8_conf1;
#endif
}
static inline void pci_set_method(device_t dev)

6
src/northbridge/amd/agesa/family10/northbridge.c
View File

@ -1142,11 +1142,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = amdfam10_domain_enable_resources,
.init = NULL,
.scan_bus = amdfam10_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};

7
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -863,12 +863,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = domain_enable_resources,
.init = NULL,
.scan_bus = f15_pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};

7
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -849,12 +849,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = domain_enable_resources,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};
static void sysconf_init(device_t dev) // first node

6
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -1154,11 +1154,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = amdfam10_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};
static void sysconf_init(device_t dev) // first node

6
src/northbridge/intel/gm45/northbridge.c
View File

@ -202,11 +202,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = mch_domain_init,
.scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};

6
src/northbridge/intel/haswell/northbridge.c
View File

@ -98,11 +98,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};
static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)

6
src/northbridge/intel/i5000/northbridge.c
View File

@ -168,11 +168,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};
static void enable_dev(device_t dev)

6
src/northbridge/intel/i945/northbridge.c
View File

@ -185,11 +185,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)

6
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -289,11 +289,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)

6
src/northbridge/intel/sch/northbridge.c
View File

@ -200,11 +200,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
#endif
.ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)

3
src/northbridge/via/vx900/northbridge.c
View File

@ -304,8 +304,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
/* We always run with MMCONF enabled. */
.ops_pci_bus = &pci_ops_mmconf,
.ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)