GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

mainboard/amd/bettong: Use C89 comments style & remove commented code

Browse source 
Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-10 20:20:09 +02:00 committed by Martin Roth
parent a51d2db4f0
commit 874fe1d328
3 changed files with 3 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/amd/bettong/BiosCallOuts.c
View file

@ -72,7 +72,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) { if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->FchReset.Xhci1Enable = FALSE;
FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio;

4
src/mainboard/amd/bettong/OemCustomize.c
View file

@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
}, },
/* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
{ {
DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled, HotplugDisabled,
@ -91,7 +91,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
}, },
/* DP1 */ /* DP1 */
{ {
0, //DESCRIPTOR_TERMINATE_LIST, 0, /*DESCRIPTOR_TERMINATE_LIST, */
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
}, },

1
src/mainboard/amd/bettong/mptable.c
View file

@ -64,7 +64,6 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc); smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI "); my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02; bus_isa = 0x02;