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soc/amd: factor out SMBUS controller registers into common header 

The patch also rewrites the bit definition using shifts to make them
easier to read.

The older non-SoC chips can probably also use the new header file, but
for this patch the scope is limited to soc/amd, since the older non-SoC
chips don't use the SMBUS controller code in soc/amd/common.

TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change.

Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2020-12-01 00:34:11 +01:00
parent 6443ad4a53
commit 875e5aa96c
6 changed files with 53 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
src/soc/amd/common/block/include/amdblocks/smbus.h Normal file
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@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef AMD_BLOCK_SMBUS_H
#define AMD_BLOCK_SMBUS_H
/* SMBUS MMIO offsets 0xfed80a00 */
#define SMBHSTSTAT 0x0
#define SMBHST_STAT_FAILED (1 << 4)
#define SMBHST_STAT_COLLISION (1 << 3)
#define SMBHST_STAT_ERROR (1 << 2)
#define SMBHST_STAT_INTERRUPT (1 << 1)
#define SMBHST_STAT_BUSY (1 << 0)
#define SMBHST_STAT_CLEAR 0xff
#define SMBHST_STAT_NOERROR (1 << 1) /* TODO: this one looks odd */
#define SMBHST_STAT_VAL_BITS 0x1f
#define SMBHST_STAT_ERROR_BITS 0x1c
#define SMBSLVSTAT 0x1
#define SMBSLV_STAT_ALERT (1 << 5)
#define SMBSLV_STAT_SHADOW2 (1 << 4)
#define SMBSLV_STAT_SHADOW1 (1 << 3)
#define SMBSLV_STAT_SLV_STS (1 << 2)
#define SMBSLV_STAT_SLV_INIT (1 << 1)
#define SMBSLV_STAT_SLV_BUSY (1 << 0)
#define SMBSLV_STAT_CLEAR 0x1f
#define SMBHSTCTRL 0x2
#define SMBHST_CTRL_RST (1 << 7)
#define SMBHST_CTRL_STRT (1 << 6)
#define SMBHST_CTRL_QCK_RW (0x0 << 2)
#define SMBHST_CTRL_BTE_RW (0x1 << 2)
#define SMBHST_CTRL_BDT_RW (0x2 << 2)
#define SMBHST_CTRL_WDT_RW (0x3 << 2)
#define SMBHST_CTRL_BLK_RW (0x5 << 2)
#define SMBHST_CTRL_MODE_BITS (0x7 << 2)
#define SMBHST_CTRL_KILL (1 << 1)
#define SMBHST_CTRL_IEN (1 << 0)
#define SMBHSTCMD 0x3
#define SMBHSTADDR 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBHSTBLKDAT 0x7
#define SMBSLVCTRL 0x8
#define SMBSLVCMD_SHADOW 0x9
#define SMBSLVEVT 0xa
#define SMBSLVDAT 0xc
#define SMBTIMING 0xe
#endif /* AMD_BLOCK_SMBUS_H */

2
src/soc/amd/common/block/smbus/smbus.c
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@ -5,7 +5,7 @@
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio_map.h>
#include <soc/southbridge.h> #include <amdblocks/smbus.h>
/* /*
* Between 1-10 seconds, We should never timeout normally * Between 1-10 seconds, We should never timeout normally

44
src/soc/amd/picasso/include/soc/southbridge.h
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@ -93,50 +93,6 @@
#define PM_USB_ENABLE 0xef #define PM_USB_ENABLE 0xef
#define PM_USB_ALL_CONTROLLERS 0x7f #define PM_USB_ALL_CONTROLLERS 0x7f
/* SMBUS MMIO offsets 0xfed80a00 */
#define SMBHSTSTAT 0x0
#define SMBHST_STAT_FAILED BIT(4)
#define SMBHST_STAT_COLLISION BIT(3)
#define SMBHST_STAT_ERROR BIT(2)
#define SMBHST_STAT_INTERRUPT BIT(1)
#define SMBHST_STAT_BUSY BIT(0)
#define SMBHST_STAT_CLEAR 0xff
#define SMBHST_STAT_NOERROR BIT(1)
#define SMBHST_STAT_VAL_BITS 0x1f
#define SMBHST_STAT_ERROR_BITS 0x1c
#define SMBSLVSTAT 0x1
#define SMBSLV_STAT_ALERT 0x20
#define SMBSLV_STAT_SHADOW2 0x10
#define SMBSLV_STAT_SHADOW1 0x08
#define SMBSLV_STAT_SLV_STS 0x04
#define SMBSLV_STAT_SLV_INIT 0x02
#define SMBSLV_STAT_SLV_BUSY 0x01
#define SMBSLV_STAT_CLEAR 0x1f
#define SMBHSTCTRL 0x2
#define SMBHST_CTRL_RST 0x80
#define SMBHST_CTRL_STRT 0x40
#define SMBHST_CTRL_QCK_RW 0x00
#define SMBHST_CTRL_BTE_RW 0x04
#define SMBHST_CTRL_BDT_RW 0x08
#define SMBHST_CTRL_WDT_RW 0x0c
#define SMBHST_CTRL_BLK_RW 0x14
#define SMBHST_CTRL_MODE_BITS 0x1c
#define SMBHST_CTRL_KILL 0x02
#define SMBHST_CTRL_IEN 0x01
#define SMBHSTCMD 0x3
#define SMBHSTADDR 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBHSTBLKDAT 0x7
#define SMBSLVCTRL 0x8
#define SMBSLVCMD_SHADOW 0x9
#define SMBSLVEVT 0xa
#define SMBSLVDAT 0xc
#define SMBTIMING 0xe
/* FCH MISC Registers 0xfed80e00 */ /* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00 #define GPP_CLK_CNTRL 0x00
#define GPP_CLK0_REQ_SHIFT 0 #define GPP_CLK0_REQ_SHIFT 0

1
src/soc/amd/picasso/southbridge.c
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@ -17,6 +17,7 @@
#include <amdblocks/espi.h> #include <amdblocks/espi.h>
#include <amdblocks/lpc.h> #include <amdblocks/lpc.h>
#include <amdblocks/acpi.h> #include <amdblocks/acpi.h>
#include <amdblocks/smbus.h>
#include <amdblocks/spi.h> #include <amdblocks/spi.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/cpu.h> #include <soc/cpu.h>

44
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -89,50 +89,6 @@
#define PM_USB_ENABLE 0xef #define PM_USB_ENABLE 0xef
#define PM_USB_ALL_CONTROLLERS 0x7f #define PM_USB_ALL_CONTROLLERS 0x7f
/* SMBUS MMIO offsets 0xfed80a00 */
#define SMBHSTSTAT 0x0
#define SMBHST_STAT_FAILED 0x10
#define SMBHST_STAT_COLLISION 0x08
#define SMBHST_STAT_ERROR 0x04
#define SMBHST_STAT_INTERRUPT 0x02
#define SMBHST_STAT_BUSY 0x01
#define SMBHST_STAT_CLEAR 0xff
#define SMBHST_STAT_NOERROR 0x02
#define SMBHST_STAT_VAL_BITS 0x1f
#define SMBHST_STAT_ERROR_BITS 0x1c
#define SMBSLVSTAT 0x1
#define SMBSLV_STAT_ALERT 0x20
#define SMBSLV_STAT_SHADOW2 0x10
#define SMBSLV_STAT_SHADOW1 0x08
#define SMBSLV_STAT_SLV_STS 0x04
#define SMBSLV_STAT_SLV_INIT 0x02
#define SMBSLV_STAT_SLV_BUSY 0x01
#define SMBSLV_STAT_CLEAR 0x1f
#define SMBHSTCTRL 0x2
#define SMBHST_CTRL_RST 0x80
#define SMBHST_CTRL_STRT 0x40
#define SMBHST_CTRL_QCK_RW 0x00
#define SMBHST_CTRL_BTE_RW 0x04
#define SMBHST_CTRL_BDT_RW 0x08
#define SMBHST_CTRL_WDT_RW 0x0c
#define SMBHST_CTRL_BLK_RW 0x14
#define SMBHST_CTRL_MODE_BITS 0x1c
#define SMBHST_CTRL_KILL 0x02
#define SMBHST_CTRL_IEN 0x01
#define SMBHSTCMD 0x3
#define SMBHSTADDR 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBHSTBLKDAT 0x7
#define SMBSLVCTRL 0x8
#define SMBSLVCMD_SHADOW 0x9
#define SMBSLVEVT 0xa
#define SMBSLVDAT 0xc
#define SMBTIMING 0xe
/* FCH MISC Registers 0xfed80e00 */ /* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00 #define GPP_CLK_CNTRL 0x00
#define GPP_CLK2_REQ_MAP_SHIFT 8 #define GPP_CLK2_REQ_MAP_SHIFT 8

1
src/soc/amd/stoneyridge/southbridge.c
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@ -17,6 +17,7 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h> #include <amdblocks/lpc.h>
#include <amdblocks/acpi.h> #include <amdblocks/acpi.h>
#include <amdblocks/smbus.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <soc/smi.h> #include <soc/smi.h>
#include <soc/amd_pci_int_defs.h> #include <soc/amd_pci_int_defs.h>