GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arch/x86/postcar_loader.c: Change prepare_and_run_postcar signature 

The postcar frame can now be a local variable to that function.

Change-Id: I873298970fff76b9ee1cae7da156613eb557ffbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Arthur Heymans 2022-02-15 11:06:10 +01:00
parent ba00d10c41
commit 876a1b48f8
5 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/include/arch/romstage.h
View File

@ -43,7 +43,7 @@ void fill_postcar_frame(struct postcar_frame *pcf);
* prepare_and_run_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use.
*/
void prepare_and_run_postcar(struct postcar_frame *pcf);
void prepare_and_run_postcar(void);
/*
* Systems without a native coreboot cache-as-ram teardown may implement

14
src/arch/x86/postcar_loader.c
View File

@ -21,6 +21,8 @@ static size_t var_mtrr_ctx_size(void)
static int postcar_frame_init(struct postcar_frame *pcf)
{
memset(pcf, 0, sizeof(*pcf));
struct var_mtrr_context *ctx;
ctx = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, var_mtrr_ctx_size());
@ -61,16 +63,18 @@ static void run_postcar_phase(struct postcar_frame *pcf);
/* prepare_and_run_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
void prepare_and_run_postcar(struct postcar_frame *pcf)
void prepare_and_run_postcar(void)
{
if (postcar_frame_init(pcf))
struct postcar_frame pcf;
if (postcar_frame_init(&pcf))
die("Unable to initialize postcar frame.\n");
fill_postcar_frame(pcf);
fill_postcar_frame(&pcf);
postcar_frame_common_mtrrs(pcf);
postcar_frame_common_mtrrs(&pcf);
run_postcar_phase(pcf);
run_postcar_phase(&pcf);
/* We do not return here. */
}

4
src/cpu/intel/car/romstage.c
View File

@ -14,8 +14,6 @@
following as a guideline for acceptable stack usage. */
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
static struct postcar_frame early_mtrrs;
static void romstage_main(void)
{
int i;
@ -54,7 +52,7 @@ static void romstage_main(void)
if (CONFIG(SMM_TSEG))
smm_list_regions();
prepare_and_run_postcar(&early_mtrrs);
prepare_and_run_postcar();
/* We do not return here. */
}

3
src/drivers/amd/agesa/romstage.c
View File

@ -33,7 +33,6 @@ static void ap_romstage_main(void);
static void romstage_main(void)
{
struct postcar_frame pcf;
struct sysinfo romstage_state;
struct sysinfo *cb = &romstage_state;
int cbmem_initted = 0;
@ -78,7 +77,7 @@ static void romstage_main(void)
romstage_handoff_init(cb->s3resume);
prepare_and_run_postcar(&pcf);
prepare_and_run_postcar();
/* We do not return. */
}

3
src/soc/amd/stoneyridge/romstage.c
View File

@ -50,7 +50,6 @@ static void bsp_agesa_call(void)
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@ -121,7 +120,7 @@ asmlinkage void car_stage_entry(void)
smm_list_regions();
post_code(0x44);
prepare_and_run_postcar(&pcf);
prepare_and_run_postcar();
}
void fill_postcar_frame(struct postcar_frame *pcf)