diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
index bc921e3a4a..528e4de46e 100644
--- a/src/soc/intel/alderlake/bootblock/pch.c
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -9,6 +9,7 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -34,9 +35,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN         0x01
 #define PCR_PSFX_T0_SHDW_PCIEN              0x1C
 
-#define PCR_DMI_DMICTL                      0x2234
-#define  PCR_DMI_DMICTL_SRLOCK              (1 << 31)
-
 #define PCR_DMI_ACPIBA                      0x27B4
 #define PCR_DMI_ACPIBDID                    0x27B8
 #define PCR_DMI_PMBASEA                     0x27AC
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 8ebfb3dcf3..a05e56549c 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -4,6 +4,7 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -32,9 +33,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
-
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h
index b771b22022..55bf20d40d 100644
--- a/src/soc/intel/common/block/include/intelblocks/dmi.h
+++ b/src/soc/intel/common/block/include/intelblocks/dmi.h
@@ -5,6 +5,9 @@
 
 #include <types.h>
 
+#define PCR_DMI_DMICTL		0x2234
+#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
+
 /*
  * Takes base, size and destination ID and configures the GPMR
  * for accessing the region.
diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c
index e1b7d85c5a..e1414f11fe 100644
--- a/src/soc/intel/elkhartlake/bootblock/pch.c
+++ b/src/soc/intel/elkhartlake/bootblock/pch.c
@@ -5,6 +5,7 @@
 #include <device/device.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -31,9 +32,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
-
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index a6b6b20e67..08edfeec16 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -3,6 +3,7 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -27,9 +28,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
-
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index 96a7dc2b32..d98d5a8213 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -5,6 +5,7 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -31,9 +32,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
-
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 38ae916dad..a5bbb095b0 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -3,6 +3,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
@@ -20,8 +21,6 @@
 #include <soc/pmc.h>
 #include "../chip.h"
 
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 5c4d1d5fb7..5a63b40c21 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -11,6 +11,7 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -36,9 +37,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
-
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c
index 8de7743d94..44824ca651 100644
--- a/src/soc/intel/xeon_sp/pch.c
+++ b/src/soc/intel/xeon_sp/pch.c
@@ -3,6 +3,7 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
+#include <intelblocks/dmi.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/p2sb.h>
@@ -11,8 +12,6 @@
 #include <soc/pmc.h>
 #include <console/console.h>
 
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC