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spd/lp5: Generate initial SPDs for Sabrina SoC 

Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.

BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2022-02-01 22:29:57 -07:00 committed by Felix Held
parent fd07fa20da
commit 876cfe0ee2
6 changed files with 136 additions and 0 deletions
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1
spd/lp5/platforms_manifest.generated.txt
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@ -2,3 +2,4 @@
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 # util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
ADL,set-0 ADL,set-0
SBR,set-1

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spd/lp5/set-1/parts_spd_manifest.generated.txt Normal file
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# Generated by:
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
MT62F512M32D2DR-031 WT:B,spd-1.hex
MT62F1G32D4DR-031 WT:B,spd-2.hex
H9JCNNNCP3MLYR-N6E,spd-2.hex
K3LKBKB0BM-MGCP,spd-3.hex

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spd/lp5/set-1/spd-1.hex Normal file
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spd/lp5/set-1/spd-2.hex Normal file
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spd/lp5/set-1/spd-3.hex Normal file
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spd/lp5/set-1/spd-empty.hex Normal file
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