soc/intel/cannonlake: Add config for sata devslp pad reset configuration
CML FSP now provides a provision to configure the SATA devslp GPIO pad reset configuration. This config would help set the the required pad reset configuration. BUG=b:133000685 Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -136,9 +136,19 @@ struct soc_intel_cannonlake_config {
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Sata_AHCI,
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Sata_RAID,
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} SataMode;
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/* SATA devslp pad reset configuration */
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enum {
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SataDevSlpResumeReset = 1,
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SataDevSlpHostDeepReset = 3,
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SataDevSlpPlatformReset = 5,
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SataDevSlpDswReset = 7
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} SataDevSlpRstConfig;
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uint8_t SataSalpSupport;
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uint8_t SataPortsEnable[8];
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uint8_t SataPortsDevSlp[8];
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uint8_t SataPortsDevSlpResetConfig[8];
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/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
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uint8_t SlpS0WithGbeSupport;
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@ -186,6 +186,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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sizeof(params->SataPortsEnable));
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memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
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sizeof(params->SataPortsDevSlp));
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#if CONFIG(SOC_INTEL_COMETLAKE)
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memcpy(params->SataPortsDevSlpResetConfig,
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config->SataPortsDevSlpResetConfig,
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sizeof(params->SataPortsDevSlpResetConfig));
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#endif
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}
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/* Lan */
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