soc/intel/cannonlake: Add config for sata devslp pad reset configuration

CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

BUG=b:133000685

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Aamir Bohra 2019-09-10 08:39:14 +05:30 committed by Furquan Shaikh
parent 0e3c245c6c
commit 87bb5f5e7a
2 changed files with 15 additions and 0 deletions

View File

@ -136,9 +136,19 @@ struct soc_intel_cannonlake_config {
Sata_AHCI,
Sata_RAID,
} SataMode;
/* SATA devslp pad reset configuration */
enum {
SataDevSlpResumeReset = 1,
SataDevSlpHostDeepReset = 3,
SataDevSlpPlatformReset = 5,
SataDevSlpDswReset = 7
} SataDevSlpRstConfig;
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
uint8_t SataPortsDevSlpResetConfig[8];
/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
uint8_t SlpS0WithGbeSupport;

View File

@ -186,6 +186,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
#if CONFIG(SOC_INTEL_COMETLAKE)
memcpy(params->SataPortsDevSlpResetConfig,
config->SataPortsDevSlpResetConfig,
sizeof(params->SataPortsDevSlpResetConfig));
#endif
}
/* Lan */