soc/mediatek/mt8192: devapc: add basic devapc drivers
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -40,6 +40,7 @@ romstage-y += mt6359p.c
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ramstage-y += ../common/auxadc.c
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ramstage-y += ../common/ddp.c ddp.c
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ramstage-y += devapc.c
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ramstage-y += dpm.c
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ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
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ramstage-y += flash_controller.c
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@ -0,0 +1,57 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <soc/devapc.h>
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static void *getreg(uintptr_t base, unsigned int offset)
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{
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return (void *)(base + offset);
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}
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static void infra_master_init(uintptr_t base)
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{
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/* Sidband */
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SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, 1, CPU_EB_SEC, 1);
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/* Domain */
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SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1);
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SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2,
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CPU_EB_DOM, MAS_DOMAIN_2);
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}
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static void peri_master_init(uintptr_t base)
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{
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/* Domain */
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SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, MAS_DOMAIN_2);
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}
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static uintptr_t devapc_base[DEVAPC_AO_MAX] = {
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DEVAPC_INFRA_AO_BASE,
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DEVAPC_PERI_AO_BASE,
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DEVAPC_PERI2_AO_BASE,
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DEVAPC_PERI_PAR_AO_BASE,
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DEVAPC_FMEM_AO_BASE,
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};
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static void (*master_init[DEVAPC_AO_MAX])(uintptr_t) = {
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infra_master_init,
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peri_master_init,
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};
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void dapc_init(void)
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{
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int i;
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uintptr_t devapc_ao_base;
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for (i = 0; i < ARRAY_SIZE(devapc_base); i++) {
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devapc_ao_base = devapc_base[i];
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/* Init dapc */
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write32(getreg(devapc_ao_base, AO_APC_CON), 0x0);
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write32(getreg(devapc_ao_base, AO_APC_CON), 0x1);
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/* Init master */
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if (master_init[i])
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master_init[i](devapc_ao_base);
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}
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}
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@ -28,6 +28,11 @@ enum {
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PMIF_SPMI_BASE = IO_PHYS + 0x00027000,
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PMICSPI_MST_BASE = IO_PHYS + 0x00028000,
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SPMI_MST_BASE = IO_PHYS + 0x00029000,
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DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000,
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DEVAPC_PERI_AO_BASE = IO_PHYS + 0x00034000,
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DEVAPC_PERI2_AO_BASE = IO_PHYS + 0x00038000,
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DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000,
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DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000,
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I2C_DMA_BASE = IO_PHYS + 0x00217080,
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EMI_BASE = IO_PHYS + 0x00219000,
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EMI_MPU_BASE = IO_PHYS + 0x00226000,
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@ -0,0 +1,52 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_MT8192_DEVAPC_H
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#define SOC_MEDIATEK_MT8192_DEVAPC_H
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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void dapc_init(void);
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#define DEVAPC_AO_MAX 6
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enum devapc_ao_offset {
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MAS_DOM_0 = 0x0900,
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MAS_DOM_1 = 0x0904,
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MAS_SEC_0 = 0x0A00,
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AO_APC_CON = 0x0F00,
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};
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/* INFRA */
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DEFINE_BIT(SCP_SSPM_SEC, 3)
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DEFINE_BIT(CPU_EB_SEC, 4)
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DEFINE_BITFIELD(PCIE_DOM, 19, 16) /* 2 */
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DEFINE_BITFIELD(SCP_SSPM_DOM, 3, 0) /* 4 */
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DEFINE_BITFIELD(CPU_EB_DOM, 11, 8) /* 5 */
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/* PERI */
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DEFINE_BITFIELD(SPM_DOM, 3, 0) /* 0 */
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enum master_domain {
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MAS_DOMAIN_0 = 0,
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MAS_DOMAIN_1,
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MAS_DOMAIN_2,
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MAS_DOMAIN_3,
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MAS_DOMAIN_4,
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MAS_DOMAIN_5,
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MAS_DOMAIN_6,
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MAS_DOMAIN_7,
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MAS_DOMAIN_8,
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MAS_DOMAIN_9,
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MAS_DOMAIN_10,
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MAS_DOMAIN_11,
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MAS_DOMAIN_12,
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MAS_DOMAIN_13,
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MAS_DOMAIN_14,
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MAS_DOMAIN_15,
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MAS_DOMAIN_MAX,
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};
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#endif /* SOC_MEDIATEK_MT8192_DEVAPC_H */
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <soc/devapc.h>
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#include <soc/emi.h>
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#include <soc/mcupm.h>
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#include <soc/mmu_operations.h>
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@ -16,6 +17,7 @@ static void soc_read_resources(struct device *dev)
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static void soc_init(struct device *dev)
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{
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mtk_mmu_disable_l2c_sram();
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dapc_init();
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mcupm_init();
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sspm_init();
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ufs_disable_refclk();
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