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broadwell: Configure IOSF Port and Grant Count 

Synchronize the code with FRC.

Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95
Original-BUG=None
Original-TEST=Build coreboot image and run on Samus to confirm the setting
is properly applied.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3
Original-Reviewed-on: https://chromium-review.googlesource.com/219523
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kenji Chen 2014-09-24 01:18:26 +08:00 committed by Patrick Georgi
parent 274ef4186f
commit 87d4a201ab
1 changed files with 25 additions and 1 deletions
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26
src/soc/intel/broadwell/pcie.c
View File

@ -99,6 +99,27 @@ static void root_port_config_update_gbe_port(void)
}
}
static void pcie_iosf_port_grant_count(device_t dev)
{
u8 update_val;
u32 rpcd = (pci_read_config32(dev, 0xfc) > 14) & 0x3;
switch (rpcd) {
case 1:
case 3:
update_val = 0x02;
break;
case 2:
update_val = 0x22;
break;
default:
update_val = 0x00;
break;
}
RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val;
}
static void root_port_init_config(device_t dev)
{
int rp;
@ -108,7 +129,10 @@ static void root_port_init_config(device_t dev)
rpc.new_rpfn = rpc.orig_rpfn;
rpc.num_ports = NUM_ROOT_PORTS;
rpc.gbe_port = -1;
pcie_update_cfg8(dev, 0xf5, 0xa, 0x5);
/* RP0 f5[3:0] = 0101b*/
pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5);
pcie_iosf_port_grant_count(dev);
rpc.pin_ownership = pci_read_config32(dev, 0x410);
root_port_config_update_gbe_port();