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mainboard/google/kahlee: Reduce VRAM to 16MB 

It was determined through testing that 16MB of reserved VRAM is
sufficient.  Additional RAM for the graphics driver is allocated out
of system memory.

BUG=b:123579702
TEST=Boot Grunt, watch VRAM usage with graphics driver logging.

Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2019-06-10 09:35:23 -06:00
parent deb99af8a1
commit 87dcd0061a
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/kahlee/variants/aleena/devicetree.cb
View File

@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
}" }"
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB" register "uma_size" = "16 * MiB"
register "stapm_percent" = "80" register "stapm_percent" = "80"
register "stapm_time_ms" = "2500000" register "stapm_time_ms" = "2500000"
register "stapm_power_mw" = "7800" register "stapm_power_mw" = "7800"

2
src/mainboard/google/kahlee/variants/careena/devicetree.cb
View File

@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
}" }"
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB" register "uma_size" = "16 * MiB"
register "stapm_percent" = "68" register "stapm_percent" = "68"
register "stapm_time_ms" = "2500000" register "stapm_time_ms" = "2500000"
register "stapm_power_mw" = "7800" register "stapm_power_mw" = "7800"

2
src/mainboard/google/kahlee/variants/grunt/devicetree.cb
View File

@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
}" }"
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB" register "uma_size" = "16 * MiB"
register "stapm_percent" = "80" register "stapm_percent" = "80"
register "stapm_time_ms" = "2500000" register "stapm_time_ms" = "2500000"
register "stapm_power_mw" = "7800" register "stapm_power_mw" = "7800"

2
src/mainboard/google/kahlee/variants/liara/devicetree.cb
View File

@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
}" }"
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB" register "uma_size" = "16 * MiB"
register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms
register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms