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AGESA: Remove heap allocations from OemCustomize.c 

We can simply declare these structures const.

Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-09-23 14:36:16 +03:00
parent e66e39059e
commit 87df26731e
24 changed files with 643 additions and 1864 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

81
src/mainboard/amd/inagua/OemCustomize.c
View File

@ -15,38 +15,11 @@
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
{ {
0, 0,
@ -71,9 +44,9 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
{ {
0, 0,
@ -86,44 +59,18 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

41
src/mainboard/amd/olivehill/OemCustomize.c
View File

@ -14,13 +14,10 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
@ -101,7 +98,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.DdiLinkList = DdiList .DdiLinkList = DdiList
}; };
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{ {
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
@ -109,44 +105,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

54
src/mainboard/amd/parmer/OemCustomize.c
View File

@ -14,8 +14,6 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -145,54 +143,16 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
/** .Flags = DESCRIPTOR_TERMINATE_LIST,
* OemCustomizeInitEarly .SocketId = 0,
* .PciePortList = PortList,
* Description: .DdiLinkList = DdiList,
* This stub function will call the host environment through the binary block };
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (PcieComplexListPtr,
0,
sizeof(PCIe_COMPLEX_DESCRIPTOR),
&InitEarly->StdHeader);
PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST;
PcieComplexListPtr->SocketId = 0;
PcieComplexListPtr->PciePortList = PortList;
PcieComplexListPtr->DdiLinkList = DdiList;
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

72
src/mainboard/amd/persimmon/OemCustomize.c
View File

@ -15,36 +15,12 @@
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
/** static const PCIe_PORT_DESCRIPTOR PortList[] = {
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
@ -77,7 +53,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
@ -94,42 +70,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

77
src/mainboard/amd/south_station/OemCustomize.c
View File

@ -15,45 +15,17 @@
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
#if 1
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
@ -72,7 +44,6 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
#endif
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
@ -81,7 +52,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */ /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
{ {
0, 0,
@ -96,42 +67,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

81
src/mainboard/amd/thatcher/OemCustomize.c
View File

@ -14,8 +14,6 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -137,13 +135,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
}, },
}; };
static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
DESCRIPTOR_TERMINATE_LIST,
0,
&PortList[0],
&DdiList[0]
};
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{ {
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
@ -151,74 +142,16 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
/** .Flags = DESCRIPTOR_TERMINATE_LIST,
* OemCustomizeInitEarly .SocketId = 0,
* .PciePortList = PortList,
* Description: .DdiLinkList = DdiList,
* This stub function will call the host environment through the binary block };
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
VOID *TrinityPcieComplexListPtr;
VOID *TrinityPciePortPtr;
VOID *TrinityPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Trinity);
TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr,
0,
sizeof(Trinity),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr,
0,
sizeof(PortList),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr,
0,
sizeof(DdiList),
&InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

82
src/mainboard/amd/torpedo/OemCustomize.c
View File

@ -14,12 +14,8 @@
*/ */
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "amdlib.h"
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
@ -75,82 +71,16 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
static const PCIe_COMPLEX_DESCRIPTOR Llano = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
VOID *LlanoPcieComplexListPtr;
VOID *LlanoPciePortPtr;
VOID *LlanoPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Llano);
LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (LlanoPcieComplexListPtr,
0,
sizeof(Llano),
&InitEarly->StdHeader);
LibAmdMemFill (LlanoPciePortPtr,
0,
sizeof(PortList),
&InitEarly->StdHeader);
LibAmdMemFill (LlanoPcieDdiPtr,
0,
sizeof(DdiList),
&InitEarly->StdHeader);
LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader);
LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

76
src/mainboard/amd/union_station/OemCustomize.c
View File

@ -14,48 +14,19 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <string.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
#if 1
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{ {
0, 0,
@ -74,7 +45,6 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
#endif
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
@ -83,7 +53,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
@ -100,42 +70,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

75
src/mainboard/asrock/e350m1/OemCustomize.c
View File

@ -14,41 +14,12 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
@ -63,7 +34,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
@ -80,42 +51,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

39
src/mainboard/asrock/imb-a180/OemCustomize.c
View File

@ -14,8 +14,6 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -108,44 +106,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

80
src/mainboard/asus/f2a85-m/OemCustomize.c
View File

@ -15,13 +15,10 @@
#include "Porting.h" #include "Porting.h"
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
/* /*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
* *
@ -115,11 +112,11 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
}, },
}; };
static const PCIe_COMPLEX_DESCRIPTOR Trinity = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
@ -129,73 +126,10 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
VOID *TrinityPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0;
VOID *TrinityPciePortPtr;
VOID *TrinityPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Trinity);
TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr,
0,
sizeof(Trinity),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr,
0,
sizeof(PortList),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr,
0,
sizeof(DdiList),
&InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

39
src/mainboard/bap/ode_e20XX/OemCustomize.c
View File

@ -14,8 +14,6 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
@ -93,44 +91,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

40
src/mainboard/biostar/am1ml/OemCustomize.c
View File

@ -14,13 +14,10 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
@ -113,44 +110,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->IdeEnable = 0; FchReset->IdeEnable = 0;
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

73
src/mainboard/elmex/pcm205400/OemCustomize.c
View File

@ -15,36 +15,11 @@
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
@ -77,7 +52,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
@ -94,42 +69,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

75
src/mainboard/gizmosphere/gizmo/OemCustomize.c
View File

@ -15,41 +15,12 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
/*---------------------------------------------------------------------------------------*/ static const PCIe_PORT_DESCRIPTOR PortList[] = {
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
@ -82,7 +53,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
@ -99,42 +70,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

40
src/mainboard/gizmosphere/gizmo2/OemCustomize.c
View File

@ -14,13 +14,10 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
@ -102,44 +99,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

41
src/mainboard/hp/abm/OemCustomize.c
View File

@ -15,13 +15,10 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
{ {
0, 0,
@ -103,45 +100,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This is the stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

54
src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
View File

@ -15,10 +15,8 @@
#include "Porting.h" #include "Porting.h"
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
@ -146,54 +144,16 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
/** .Flags = DESCRIPTOR_TERMINATE_LIST,
* OemCustomizeInitEarly .SocketId = 0,
* .PciePortList = PortList,
* Description: .DdiLinkList = DdiList,
* This stub function will call the host environment through the binary block };
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (PcieComplexListPtr,
0,
sizeof(PCIe_COMPLEX_DESCRIPTOR),
&InitEarly->StdHeader);
PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST;
PcieComplexListPtr->SocketId = 0;
PcieComplexListPtr->PciePortList = PortList;
PcieComplexListPtr->DdiLinkList = DdiList;
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

81
src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
View File

@ -16,37 +16,11 @@
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
**/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
void *BrazosPcieComplexListPtr;
void *BrazosPciePortPtr;
void *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/**
* @brief Initialize Port descriptors
*/
PCIe_PORT_DESCRIPTOR PortList[] = {
/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
{ {
0, 0,
@ -114,10 +88,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
/** static const PCIe_DDI_DESCRIPTOR DdiList[] = {
* @brief Initialize Ddi descriptors
*/
PCIe_DDI_DESCRIPTOR DdiList[] = {
/* (DDI interface Lanes 8:11, DdA, ...) */ /* (DDI interface Lanes 8:11, DdA, ...) */
{ {
0, 0,
@ -134,46 +105,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
/** void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
* @brief GNB PCIe topology Porting {
* InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
* Allocate buffer for
* PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
*/
AllocHeapParams.RequestedBufferSize =
sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr =
(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList =
(PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList =
(PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

56
src/mainboard/lenovo/g505s/OemCustomize.c
View File

@ -15,10 +15,8 @@
#include "Porting.h" #include "Porting.h"
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
@ -139,6 +137,13 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
}, },
}; };
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList,
};
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{ {
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
@ -146,54 +151,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = FALSE; FchReset->Xhci1Enable = FALSE;
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
/* GNB PCIe topology Porting */
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (PcieComplexListPtr,
0,
sizeof(PCIe_COMPLEX_DESCRIPTOR),
&InitEarly->StdHeader);
PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST;
PcieComplexListPtr->SocketId = 0;
PcieComplexListPtr->PciePortList = PortList;
PcieComplexListPtr->DdiLinkList = DdiList;
InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

75
src/mainboard/lippert/frontrunner-af/OemCustomize.c
View File

@ -14,41 +14,12 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
@ -81,7 +52,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
@ -98,42 +69,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

75
src/mainboard/lippert/toucan-af/OemCustomize.c
View File

@ -14,41 +14,12 @@
*/ */
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include "heapManager.h"
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
@ -81,7 +52,7 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
{ {
0, 0,
@ -98,42 +69,16 @@ PCIe_DDI_DESCRIPTOR DdiList[] = {
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
// GNB PCIe topology Porting void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
// InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

78
src/mainboard/msi/ms7721/OemCustomize.c
View File

@ -16,10 +16,8 @@
#include "Porting.h" #include "Porting.h"
#include "AGESA.h" #include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
@ -122,11 +120,11 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
}, },
}; };
static const PCIe_COMPLEX_DESCRIPTOR Trinity = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
DESCRIPTOR_TERMINATE_LIST, .Flags = DESCRIPTOR_TERMINATE_LIST,
0, .SocketId = 0,
&PortList[0], .PciePortList = PortList,
&DdiList[0] .DdiLinkList = DdiList,
}; };
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
@ -136,73 +134,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
} }
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{ {
AGESA_STATUS Status; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
VOID *TrinityPcieComplexListPtr;
VOID *TrinityPciePortPtr;
VOID *TrinityPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Trinity);
TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr,
0,
sizeof(Trinity),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr,
0,
sizeof(PortList),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr,
0,
sizeof(DdiList),
&InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
} }
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

80
src/mainboard/pcengines/apu1/OemCustomize.c
View File

@ -16,35 +16,11 @@
#include "PlatformGnbPcieComplex.h" #include "PlatformGnbPcieComplex.h"
#include <string.h> #include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
/** static const PCIe_PORT_DESCRIPTOR PortList[] = {
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
VOID *BrazosPciePortPtr;
VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{ {
0, 0,
@ -77,52 +53,16 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) .Flags = DESCRIPTOR_TERMINATE_LIST,
{ .SocketId = 0,
DESCRIPTOR_TERMINATE_LIST, .PciePortList = PortList,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), .DdiLinkList = NULL,
//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
{ConnectorTypeDP, Aux1, Hdp1}
},
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
DESCRIPTOR_TERMINATE_LIST, {
0, InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
&PortList[0],
&DdiList[0]
};
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }