diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 97a1780717..c42f400362 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -90,7 +90,7 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.relocation_handler = relocation_handler,
-	.post_mp_init = enable_smi_generation,
+	.post_mp_init = global_smi_enable,
 };
 
 void mp_init_cpus(struct bus *cpu_bus)
diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h
index 8c71c66aec..02a23f58a2 100644
--- a/src/soc/amd/picasso/include/soc/smi.h
+++ b/src/soc/amd/picasso/include/soc/smi.h
@@ -220,6 +220,4 @@ void disable_gevent_smi(uint8_t gevent);
 void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
 void soc_route_sci(uint8_t event);
 
-void enable_smi_generation(void);
-
 #endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */
diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c
index 994a1692cf..ba36e65da6 100644
--- a/src/soc/amd/picasso/smi.c
+++ b/src/soc/amd/picasso/smi.c
@@ -17,7 +17,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 }
 
 /** Set the EOS bit and enable SMI generation from southbridge */
-void enable_smi_generation(void)
+void global_smi_enable(void)
 {
 	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
 	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 9189cfb8c1..c898ff7f93 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -90,7 +90,7 @@ static const struct mp_ops mp_ops = {
 	.get_cpu_count = get_cpu_count,
 	.get_smm_info = get_smm_info,
 	.relocation_handler = relocation_handler,
-	.post_mp_init = enable_smi_generation,
+	.post_mp_init = global_smi_enable,
 };
 
 void mp_init_cpus(struct bus *cpu_bus)
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 9268341f99..a58488ba3c 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -220,6 +220,4 @@ void disable_gevent_smi(uint8_t gevent);
 void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
 void soc_route_sci(uint8_t event);
 
-void enable_smi_generation(void);
-
 #endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
index 17836464b2..a3473aafc5 100644
--- a/src/soc/amd/stoneyridge/smi.c
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -16,7 +16,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 }
 
 /** Set the EOS bit and enable SMI generation from southbridge */
-void enable_smi_generation(void)
+void global_smi_enable(void)
 {
 	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
 	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */