From 87f20739bbdf8c8bd2195ad7d836721e08d133f3 Mon Sep 17 00:00:00 2001 From: Jason Glenesk Date: Fri, 11 Jun 2021 12:09:20 -0700 Subject: [PATCH] mb/google/guybrush: Enable STT in device tree Enable Skin Temperature Tracking with initial configuration settings. BUG=b:190732595 TEST=Confirm that AGT tool can successfully complete data collection Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Signed-off-by: Jason Glenesk Reviewed-on: https://review.coreboot.org/c/coreboot/+/55434 Reviewed-by: Rob Barnes Reviewed-by: Matt Papageorge Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- .../guybrush/variants/baseboard/devicetree.cb | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 59efa43279..df8bd2afd3 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -48,6 +48,28 @@ chip soc/amd/cezanne # Enable S0i3 support register "s0ix_enable" = "1" + # Enable STT support + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_min_limit" = "0" + register "stt_m1" = "0x0319" + register "stt_m2" = "0x01A0" + register "stt_m3" = "0" + register "stt_m4" = "0" + register "stt_m5" = "0" + register "stt_m6" = "0" + register "stt_c_apu" = "0xE99F" + register "stt_c_gpu" = "0" + register "stt_c_hs2" = "0" + register "stt_alpha_apu" = "0xCCD" + register "stt_alpha_gpu" = "0" + register "stt_alpha_hs2" = "0" + register "stt_skin_temp_apu" = "0x2D00" + register "stt_skin_temp_gpu" = "0" + register "stt_skin_temp_hs2" = "0" + register "stt_error_coeff" = "0xD" + register "stt_error_rate_coefficient" = "0x8F6" + register "system_configuration" = "2" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |