soc/intel/skylake: add acoustic noise mitigation params for FSP 1.1
Adapted from Chromium commit d6655eb [Skylake: create UPD Interface for acoustic noise tuning] Add FSP 1.1 params needed for acoustic mitigation on google/caroline (to be upstreamed in a subsequent commit). TEST: build/boot google/caroline Change-Id: Ifb36ecef8c1735c63a5322d952929e9c34cddfb9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -196,6 +196,13 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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params->SendVrMbxCmd = config->SendVrMbxCmd;
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/* Acoustic Noise Mitigation */
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params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
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params->SlowSlewRateForIa = config->SlowSlewRateForIa;
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params->SlowSlewRateForGt = config->SlowSlewRateForGt;
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params->SlowSlewRateForSa = config->SlowSlewRateForSa;
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params->FastPkgCRampDisable = config->FastPkgCRampDisable;
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soc_irq_settings(params);
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}
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@ -801,6 +808,21 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
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fsp_display_upd_value("SendVrMbxCmd", 1,
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original->SendVrMbxCmd,
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params->SendVrMbxCmd);
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fsp_display_upd_value("AcousticNoiseMitigation", 1,
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original->AcousticNoiseMitigation,
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params->AcousticNoiseMitigation);
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fsp_display_upd_value("SlowSlewRateForIa", 1,
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original->SlowSlewRateForIa,
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params->SlowSlewRateForIa);
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fsp_display_upd_value("SlowSlewRateForGt", 1,
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original->SlowSlewRateForGt,
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params->SlowSlewRateForGt);
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fsp_display_upd_value("SlowSlewRateForSa", 1,
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original->SlowSlewRateForSa,
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params->SlowSlewRateForSa);
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fsp_display_upd_value("FastPkgCRampDisable", 1,
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original->FastPkgCRampDisable,
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params->FastPkgCRampDisable);
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}
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static void pci_set_subsystem(device_t dev, unsigned int vendor,
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@ -485,6 +485,9 @@ struct soc_intel_skylake_config {
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* 0b - Enabled
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* 1b - Disabled
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*/
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/* FSP 1.1 */
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u8 FastPkgCRampDisable;
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/* FSP 2.0 */
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u8 FastPkgCRampDisableIa;
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u8 FastPkgCRampDisableGt;
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u8 FastPkgCRampDisableSa;
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -950,14 +950,34 @@ typedef struct {
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UINT8 Early8254ClockGatingEnable;
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/** Offset 0x03E5 - Enable VR specific mailbox command
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When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. This for FSP only. 0 - Don't Send, 1 - Send
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VR specific mailbox commands, 000b: no VR specific command sent, 001b: A VR mailbox command specifically for the MPS IMPV8 VR will be sent, 010b: VR specific command sent for PS4 exit issue, 011b: VR specific command sent for both MPS IMPV8 & PS4 exit issue.
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$EN_DIS
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**/
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UINT8 SendVrMbxCmd;
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/** Offset 0x03E6
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**/
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UINT8 ReservedSiliconInitUpd[20];
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UINT8 AcousticNoiseMitigation;
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/** Offset 0x03E7
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**/
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UINT8 SlowSlewRateForIa;
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/** Offset 0x03E8
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**/
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UINT8 SlowSlewRateForGt;
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/** Offset 0x03E9
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**/
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UINT8 SlowSlewRateForSa;
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/** Offset 0x03EA
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**/
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UINT8 FastPkgCRampDisable;
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/** Offset 0x03EB
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**/
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UINT8 ReservedSiliconInitUpd[15];
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} SILICON_INIT_UPD;
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#define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */
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