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mb/asus/p5gc-mx: Remove extra BSEL strap check 

This extra check is based on comparing CPU BSEL pins and reports in
MCH configuration. This gives false positives in the case of 1333MHz
CPUs which automatically get downgraded to 1067MHz by the northbridge
(max supported frequency by 945gc).

TESTED with Intel Xeon 5460 (does not boot but completes raminit)

Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17997
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Arthur Heymans 2016-12-30 18:52:53 +01:00 committed by Martin Roth
parent de47fc3317
commit 87fff20356
1 changed files with 1 additions and 6 deletions
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7
src/mainboard/asus/p5gc-mx/romstage.c
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@ -242,12 +242,7 @@ void mainboard_romstage_entry(unsigned long bist)
i945_early_initialization(); i945_early_initialization();
m_bsel = MCHBAR32(CLKCFG) & 7; m_bsel = MCHBAR32(CLKCFG) & 7;
printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel); printk(BIOS_DEBUG, "CPU BSEL: 0x%x\nMCH BSEL: 0x%x\n", c_bsel, m_bsel);
if (c_bsel != m_bsel) { /* Should not happen */
printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n");
outb(0xe, 0xcf9);
halt();
}
s3resume = southbridge_detect_s3_resume(); s3resume = southbridge_detect_s3_resume();