mb/google/brya: Add GPIO table for nissa
Fill in the nissa baseboard GPIO table based on the nivviks P0 and
nereid P0 schematics. Also, add an override GPIO table for each of
nivviks and nereid.
The differences between nivviks and nereid are:
- WFC: nivviks has a MIPI WFC and nereid has a USB WFC, so the
MIPI-related pins are overriden to NC on nereid.
- The DMIC pins and speaker I2S pins were swapped after nivviks P0. The
baseboard reflects the new configuration, which will be used in
nivviks P1 onwards, nereid, and future variants. For now, nivviks
overrides the pins to the old configuration. Once nivviks P1 is
released, this will need to be updated to handle both.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: Ic923fd22abcaf7da0c607f66705a6e16c14cf8f2
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Reka Norman
Felix Held
parent
687793d3c0
commit
880f70660d
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@ -8,12 +8,406 @@
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* TODO */
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/* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
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/* A0 : ESPI_IO0 ==> ESPI_SOC_D0_EC */
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/* A1 : ESPI_IO1 ==> ESPI_SOC_D1_EC */
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/* A2 : ESPI_IO2 ==> ESPI_SOC_D2_EC */
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/* A3 : ESPI_IO3 ==> ESPI_SOC_D3_EC */
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/* A4 : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
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/* A5 : ESPI_ALERT0# ==> NC */
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PAD_NC(GPP_A5, NONE),
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/* A6 : ESPI_ALERT1# ==> NC */
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PAD_NC(GPP_A6, NONE),
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/* A7 : NC */
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PAD_NC(GPP_A7, NONE),
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/* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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/* A9 : ESPI_CLK ==> ESPI_SOC_CLK */
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/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
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/* A11 : GPP_A11 ==> EN_SPK_PA */
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PAD_CFG_GPO(GPP_A11, 1, DEEP),
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/* A12 : NC */
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PAD_NC(GPP_A12, NONE),
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* A14 : USB_OC1# ==> NC */
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PAD_NC(GPP_A14, NONE),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC(GPP_A15, NONE),
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/* A16 : USB_OC3# ==> NC */
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PAD_NC(GPP_A16, NONE),
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/* A17 : NC */
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PAD_NC(GPP_A17, NONE),
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/* A18 : NC */
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PAD_NC(GPP_A18, NONE),
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/* A19 : NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD */
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
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/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
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/* A23 : GPP_A23 ==> HP_INT_ODL */
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PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH),
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/* B0 : CORE_VID0 ==> VCCIN_AUX_VID0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1 : CORE_VID1 ==> VCCIN_AUX_VID1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2 : NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : NC */
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PAD_NC(GPP_B3, NONE),
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/* B4 : NC */
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PAD_NC(GPP_B4, NONE),
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/* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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/* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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/* B7 : I2C3_SDA ==> SOC_I2C_AUDIO_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* B8 : I2C3_SCL ==> SOC_I2C_AUDIO_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/* B9 : Not available */
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PAD_NC(GPP_B9, NONE),
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/* B10 : Not available */
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PAD_NC(GPP_B10, NONE),
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/* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */
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PAD_CFG_GPO(GPP_B11, 1, DEEP),
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/* B12 : SLP_S0# ==> SLP_S0_L */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLTRST# ==> PLT_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : SPKR ==> GPP_B14_STRAP */
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PAD_NC(GPP_B14, NONE),
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/* B15 : NC */
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PAD_NC(GPP_B15, NONE),
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/* B16 : I2C5_SDA ==> SOC_I2C_TCHPAD_SDA */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
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/* B17 : I2C5_SCL ==> SOC_I2C_TCHPAD_SCL */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
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/* B18 : GPP_B18 ==> GPP_B18_STRAP */
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PAD_NC(GPP_B18, NONE),
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/* B19 : Not available */
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PAD_NC(GPP_B19, NONE),
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/* B20 : Not available */
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PAD_NC(GPP_B20, NONE),
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/* B21 : Not available */
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PAD_NC(GPP_B21, NONE),
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/* B22 : Not available */
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PAD_NC(GPP_B22, NONE),
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/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
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PAD_NC(GPP_B23, NONE),
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_C1, 0, DEEP),
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/* C2 : SMBALERT# ==> GPP_C2_STRAP */
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PAD_NC(GPP_C2, NONE),
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/* C3 : SML0CLK ==> EN_PP3300_UCAM_X */
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PAD_CFG_GPO(GPP_C3, 1, DEEP),
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/* C4 : NC */
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PAD_NC(GPP_C4, NONE),
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/* C5 : SML0ALERT# ==> GPP_C5_STRAP */
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PAD_NC(GPP_C5, NONE),
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/* C6 : SML1CLK ==> TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_C6, 0, DEEP),
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/* C7 : SML1DATA ==> TCHSCR_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
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/* D0 : NC */
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PAD_NC(GPP_D0, NONE),
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/* D1 : NC */
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PAD_NC(GPP_D1, NONE),
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/* D2 : NC */
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PAD_NC(GPP_D2, NONE),
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/* D3 : ISH_GP3 ==> WCAM_RST_L */
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PAD_CFG_GPO(GPP_D3, 0, DEEP),
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/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_D4, 1, DEEP),
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/* D5 : NC */
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PAD_NC(GPP_D5, NONE),
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 1, DEEP),
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/* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* D9 : NC */
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PAD_NC(GPP_D9, NONE),
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/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
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PAD_NC(GPP_D10, NONE),
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/* D11 : NC */
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PAD_NC(GPP_D11, NONE),
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/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
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PAD_NC(GPP_D12, NONE),
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/* D13 : NC */
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PAD_NC(GPP_D13, NONE),
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/* D14 : NC */
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PAD_NC(GPP_D14, NONE),
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/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
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PAD_CFG_GPO(GPP_D15, 0, DEEP),
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/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
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PAD_CFG_GPO(GPP_D16, 0, DEEP),
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/* D17 : NC */
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PAD_NC(GPP_D17, NONE),
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/* D18 : NC */
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PAD_NC(GPP_D18, NONE),
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/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* E0 : NC */
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PAD_NC(GPP_E0, NONE),
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/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_E1, NONE, DEEP),
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/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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/* E3 : PROC_GP0 ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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/* E4 : NC */
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PAD_NC(GPP_E4, NONE),
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/* E5 : NC */
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PAD_NC(GPP_E5, NONE),
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/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
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PAD_NC(GPP_E6, NONE),
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/* E7 : NC */
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PAD_NC(GPP_E7, NONE),
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/* E8 : GPP_E8 ==> WLAN_DISABLE_L */
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PAD_CFG_GPO(GPP_E8, 1, DEEP),
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/* E9 : NC */
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PAD_NC(GPP_E9, NONE),
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/* E10 : NC */
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PAD_NC(GPP_E10, NONE),
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/* E11 : NC */
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PAD_NC(GPP_E11, NONE),
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/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
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/* E13 : NC */
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PAD_NC(GPP_E13, NONE),
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/* E14 : DDSP_HPDA ==> EDP_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : NC */
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PAD_NC(GPP_E15, NONE),
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/* E16 : NC */
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PAD_NC(GPP_E16, NONE),
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/* E17 : NC */
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PAD_NC(GPP_E17, NONE),
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/* E18 : NC */
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PAD_NC(GPP_E18, NONE),
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/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
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PAD_NC(GPP_E19, NONE),
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/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
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PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
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/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
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PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
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/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
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/* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */
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PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
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/* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
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PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
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/* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */
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PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
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/* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
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/* F5 : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
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/* F6 : CNV_PA_BLANKING ==> WLAN_WWAN_COEX_3 */
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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/* F7 : GPP_F7 ==> GPP_F7_STRAP */
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PAD_NC(GPP_F7, NONE),
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/* F8 : Not available */
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PAD_NC(GPP_F8, NONE),
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/* F9 : Not available */
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PAD_NC(GPP_F9, NONE),
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/* F10 : GPP_F10 ==> GPP_F10_STRAP */
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PAD_NC(GPP_F10, NONE),
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/* F11 : NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : GSXDOUT ==> WWAN_RST_L */
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PAD_CFG_GPO(GPP_F12, 0, DEEP),
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/* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_F13, NONE, DEEP),
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/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT),
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/* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI(GPP_F15, NONE, DEEP, EDGE_SINGLE, NONE),
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/* F16 : NC */
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PAD_NC(GPP_F16, NONE),
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/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
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PAD_CFG_GPI_SCI(GPP_F17, NONE, DEEP, LEVEL, INVERT),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* F19 : Not available */
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PAD_NC(GPP_F19, NONE),
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/* F20 : Not available */
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PAD_NC(GPP_F20, NONE),
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/* F21 : Not available */
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PAD_NC(GPP_F21, NONE),
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/* F22 : NC */
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PAD_NC(GPP_F22, NONE),
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/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
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PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
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/* H0 : GPP_H0_STRAP */
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PAD_NC(GPP_H0, NONE),
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/* H1 : GPP_H1_STRAP */
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PAD_NC(GPP_H1, NONE),
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/* H2 : GPP_H2_STRAP */
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PAD_NC(GPP_H2, NONE),
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/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_H3, NONE, DEEP, EDGE_SINGLE),
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/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H8 : CNV_MFUART2_RXD ==> WLAN_WWAN_COEX_1 */
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
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/* H9 : CNV_MFUART2_TXD ==> WLAN_WWAN_COEX_2 */
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
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/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H12 : UART0_RTS# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H12, 1, DEEP),
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/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* H14 : Not available */
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PAD_NC(GPP_H14, NONE),
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/* H15 : NC */
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PAD_NC(GPP_H15, NONE),
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/* H16 : Not available */
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PAD_NC(GPP_H16, NONE),
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/* H17 : NC */
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PAD_NC(GPP_H17, NONE),
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/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H19 : SRCCLKREQ4# ==> SOC_I2C_SUB_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
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/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
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PAD_CFG_GPO(GPP_H20, 1, DEEP),
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/* H21 : NC */
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PAD_NC(GPP_H21, NONE),
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/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
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PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
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/* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */
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PAD_CFG_GPO(GPP_H23, 1, DEEP),
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/* R0 : I2S0_SCLK ==> I2S_HP_BCLK_R */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
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/* R1 : I2S0_SFRM ==> I2S_HP_LRCK_R */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
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/* R2 : I2S0_TXD ==> I2S_HP_AUDIO_STRAP */
|
||||
PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
|
||||
/* R3 : I2S0_RXD ==> I2S_HP_MIC */
|
||||
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
|
||||
/* R4 : DMIC_CLK_A_0A ==> DMIC_UCAM_CLK_R */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
|
||||
/* R5 : DMIC_DATA_0A ==> DMIC_UCAM_DATA */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
|
||||
/* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
|
||||
/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
|
||||
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
|
||||
|
||||
/* S0 : I2S1_SCLK ==> I2S_SPK_BCLK_R */
|
||||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
|
||||
/* S1 : I2S1_SFRM ==> I2S_SPK_LRCK_R */
|
||||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
|
||||
/* S2 : I2S1_TXD ==> I2S_SPK_AUDIO_R */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
|
||||
/* S3 : I2S1_RXD ==> NC */
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
/* S4 : NC */
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
/* S5 : NC */
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
/* S6 : NC */
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
/* S7 : NC */
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* I5 : NC */
|
||||
PAD_NC(GPP_I5, NONE),
|
||||
/* I7 : EMMC_CMD ==> EMMC_CMD */
|
||||
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
|
||||
/* I8 : EMMC_DATA0 ==> EMMC_D0 */
|
||||
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
|
||||
/* I9 : EMMC_DATA1 ==> EMMC_D1 */
|
||||
PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
|
||||
/* I10 : EMMC_DATA2 ==> EMMC_D2 */
|
||||
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
|
||||
/* I11 : EMMC_DATA3 ==> EMMC_D3 */
|
||||
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
|
||||
/* I12 : EMMC_DATA4 ==> EMMC_D4 */
|
||||
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
|
||||
/* I13 : EMMC_DATA5 ==> EMMC_D5 */
|
||||
PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
|
||||
/* I14 : EMMC_DATA6 ==> EMMC_D6 */
|
||||
PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
|
||||
/* I15 : EMMC_DATA7 ==> EMMC_D7 */
|
||||
PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
|
||||
/* I16 : EMMC_RCLK ==> EMMC_RCLK */
|
||||
PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
|
||||
/* I17 : EMMC_CLK ==> EMMC_CLK */
|
||||
PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
|
||||
/* I18 : EMMC_RESET# ==> EMMC_RST_L */
|
||||
PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
|
||||
|
||||
/* GPD0 : BATLOW# ==> SOC_BATLOW_L */
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
/* GPD1 : ACPRESENT ==> SOC_ACPRESENT */
|
||||
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||
/* GPD2 : EC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* GPD3 : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
|
||||
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||
/* GPD4 : SLP_S3# ==> SLP_S3_L */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
/* GPD5 : SLP_S4# ==> SLP_S4_L */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
/* GPD6 : SLP_A# ==> NC */
|
||||
PAD_NC(GPD6, NONE),
|
||||
/* GPD7 : GPD7_STRAP */
|
||||
PAD_NC(GPD7, NONE),
|
||||
/* GPD8 : SUSCLK ==> PCH_SUSCLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* GPD9 : NC */
|
||||
PAD_NC(GPD9, NONE),
|
||||
/* GPD10 : SLP_S5# ==> NC */
|
||||
PAD_NC(GPD10, NONE),
|
||||
/* GPD11 : NC */
|
||||
PAD_NC(GPD11, NONE),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* TODO */
|
||||
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
const struct pad_config *__weak variant_gpio_table(size_t *num)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
bootblock-y += gpio.c
|
||||
romstage-y += gpio.c
|
||||
ramstage-y += gpio.c
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config override_gpio_table[] = {
|
||||
/* D3 : WCAM_RST_L */
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
/* D15 : EN_PP2800_WCAM_X */
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
/* D16 : EN_PP1800_PP1200_WCAM_X */
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
/* H22 : WCAM_MCLK_R */
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_override_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(override_gpio_table);
|
||||
return override_gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
bootblock-y += gpio.c
|
||||
romstage-y += gpio.c
|
||||
ramstage-y += gpio.c
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config override_gpio_table[] = {
|
||||
/* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
|
||||
/* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */
|
||||
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
|
||||
/* R6 : I2S2_TXD ==> I2S_SPK_AUDIO_R */
|
||||
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
|
||||
/* R7 : I2S2_RXD ==> NC */
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
/* S0 : NC */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
/* S1 : NC */
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
/* S2 : DMIC_CKL_A_0 ==> DMIC_UCAM_CLK_R */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
|
||||
/* S3 : DMIC_DATA_0 ==> DMIC_UCAM_DATA */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
|
||||
/* S6 : DMIC_CLK_A_1 ==> DMIC_WCAM_CLK_R */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
|
||||
/* S7 : DMIC_DATA_1 ==> DMIC_WCAM_DATA */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
|
||||
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_override_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(override_gpio_table);
|
||||
return override_gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
Loading…
Reference in New Issue