mainboard/google: Allow Hatch variants to read SPD data over SMBus

All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus. This romstage variant allows for reading the SPD data over
SMBus.

V.2: Dispence with memcpy().
V.3: Revert back to previous patch with memcpy().
V.4: Rewrite again to avoid memcpy().

BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/hatch/Kconfig

@@ -60,7 +60,11 @@ config DIMM_SPD_SIZE
 
 config ROMSTAGE_SPD_CBFS
 	bool
-	default y
+	default y if !ROMSTAGE_SPD_SMBUS
+
+config ROMSTAGE_SPD_SMBUS
+	bool
+	default n
 
 config DRIVER_TPM_SPI_BUS
 	default 0x1

src/mainboard/google/hatch/Makefile.inc

@@ -21,6 +21,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
 
 romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
+romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c

src/mainboard/google/hatch/romstage_spd_smbus.c

@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	struct cnl_mb_cfg memcfg;
+	variant_memory_params(&memcfg);
+
+	/* Read spd block to get memory config */
+	struct spd_block blk = {
+		.addr_map = { 0x50, 0x52, },
+	};
+
+	/* Access memory info through SMBUS. */
+	get_spd_smbus(&blk);
+	memcfg.spd[0].read_type = READ_SPD_MEMPTR;
+	memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len;
+	memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0];
+
+	memcfg.spd[1].read_type = NOT_EXISTING;
+
+	memcfg.spd[2].read_type = READ_SPD_MEMPTR;
+	memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len;
+	memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1];
+
+	memcfg.spd[3].read_type = NOT_EXISTING;
+	dump_spd_info(&blk);
+
+	/* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */
+	memcfg.vref_ca_config = 2;
+
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}