treewide: Include <device/mmio.h> instead of <arch/mmio.h>

<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes

Also sort includes while on it.

Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/device/xhci.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <arch/mmio.h>
 #include <console/console.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/xhci.h>
 #include <string.h>

src/drivers/emulation/qemu/bochs.c

@@ -1,16 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
 #include <arch/io.h>
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci.h>
-#include <device/pci_ops.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <framebuffer_info.h>
 #include <pc80/vga.h>
 #include <pc80/vga_io.h>
-#include <framebuffer_info.h>
+#include <stdint.h>
 
 /* VGA init. We use the Bochs VESA VBE extensions  */
 #define VBE_DISPI_IOPORT_INDEX          0x01CE

src/drivers/intel/ptt/ptt.c

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
-#include <soc/pci_devs.h>
-#include <device/pci_ops.h>
 #include <console/console.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
 #include <security/intel/txt/txt_register.h>
+#include <soc/pci_devs.h>
 #include <stdint.h>
 
 #include "ptt.h"

src/drivers/siemens/nc_fpga/nc_fpga_early.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
+#include <device/mmio.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>

src/include/cpu/x86/lapic.h

@@ -3,10 +3,10 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
-#include <arch/mmio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
+#include <device/mmio.h>
 #include <halt.h>
 #include <stdint.h>
 

src/mainboard/google/dedede/fw_config.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <bootstate.h>
+#include <device/mmio.h>
 #include <fw_config.h>
 #include <gpio.h>
 #include <intelblocks/gpio.h>

src/mainboard/google/dedede/variants/bugzzy/ramstage.c

@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <bootstate.h>
-#include <arch/mmio.h>
-#include <delay.h>
 #include <bootmode.h>
+#include <bootstate.h>
+#include <delay.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci.h>
-#include <soc/pci_devs.h>
 #include <drivers/intel/gma/i915_reg.h>
+#include <soc/pci_devs.h>
 
 static void panel_power_on(uintptr_t igd_bar)
 {

src/mainboard/protectli/vault_bsw/mainboard.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <arch/mmio.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <soc/iomap.h>
 
 #define BIOS_CONTROL_REG	0xFC

src/mainboard/scaleway/tagada/hsio.c

@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <console/console.h>
-#include <hsio.h>
+#include <device/mmio.h>
+#include <fast_spi_def.h>
 #include <gpio_defs.h>
+#include <hsio.h>
 #include <soc/fiamux.h>
 #include <string.h>
-#include <fast_spi_def.h>
 
 #ifdef __RAMSTAGE__
 static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config)

src/mainboard/siemens/mc_ehl/romstage_fsp_params.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <baseboard/variants.h>
 #include <console/console.h>
 #include <device/dram/common.h>
+#include <device/mmio.h>
 #include <hwilib.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>

src/northbridge/intel/x4x/bootblock.c

@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/bootblock.h>
-#include <arch/mmio.h>
 #include <assert.h>
+#include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <types.h>
 

src/security/intel/txt/common.c

@@ -1,12 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
-#include <console/console.h>
 #include <cbfs.h>
+#include <console/console.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <device/mmio.h>
 #include <lib.h>
 #include <smp/node.h>
 #include <string.h>

src/security/intel/txt/logging.c

@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
+#include <device/mmio.h>
 #include <types.h>
 
 #include "txt.h"

src/security/intel/txt/ramstage.c

@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <arch/mmio.h>
 #include <bootmem.h>
 #include <bootstate.h>
 #include <cbfs.h>
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/smm.h>
+#include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <security/intel/cbnt/cbnt.h>
 #include <types.h>

src/security/intel/txt/romstage.c

@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/cpu.h>
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/msr.h>
+#include <device/mmio.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <timer.h>
 #include <types.h>

src/soc/amd/common/block/acpi/ivrs.c

@@ -6,11 +6,11 @@
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/ioapic.h>
 #include <arch/ioapic.h>
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <cpu/amd/cpuid.h>
 #include <cpu/amd/msr.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <soc/acpi.h>

src/soc/amd/common/block/psp/psb.c

@@ -1,12 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
-#include <bootstate.h>
 #include <amdblocks/reset.h>
 #include <amdblocks/smn.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <cpu/amd/msr.h>
+#include <device/mmio.h>
 #include <types.h>
+
 #include "psp_def.h"
 
 #define PSB_STATUS_OFFSET	0x10994

src/soc/amd/common/block/psp/psp_efs.c

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/psp_efs.h>
-#include <arch/mmio.h>
 #include <assert.h>
 #include <boot_device.h>
 #include <commonlib/region.h>
+#include <device/mmio.h>
 #include <types.h>
 
 static struct embedded_firmware *efs;

src/soc/amd/common/block/spi/fch_spi.c

@@ -4,8 +4,8 @@
 #include <amdblocks/lpc.h>
 #include <amdblocks/psp_efs.h>
 #include <amdblocks/spi.h>
-#include <arch/mmio.h>
 #include <console/console.h>
+#include <device/mmio.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <stdint.h>

src/soc/amd/picasso/agesa_acpi.c

@@ -7,11 +7,11 @@
 #include <amdblocks/cpu.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/ioapic.h>
-#include <arch/mmio.h>
 #include <cpu/amd/cpuid.h>
 #include <cpu/amd/msr.h>
 #include <cpu/cpu.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <FspGuids.h>

src/soc/intel/alderlake/bootblock/update_descriptor.c

@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <arch/mmio.h>
 #include <cf9_reset.h>
 #include <commonlib/region.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/cpu_ids.h>
+#include <device/mmio.h>
 #include <fmap.h>
 #include <intelblocks/pmclib.h>
 #include <soc/bootblock.h>

src/southbridge/intel/lynxpoint/uart_init.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/io.h>
-#include <arch/mmio.h>
 #include <assert.h>
 #include <console/uart.h>
+#include <device/mmio.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <southbridge/intel/lynxpoint/iobp.h>