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src/mb/asrock/g41c-gs: Add variant g41m-s3 

This board is pretty much like the G41M-GS, but with DDR3 memory
instead. The PCB layout is almost identical.

What works:
 - S3/S4 resume
 - RAM init
 - Booting to Debian
 - Display lights up w/ libgfxinit
 - Both PS/2 work
 - Ethernet
 - Graphics card on PEG
 - USB
 - SATA ports
 - NVRAM debug_level
 - Internal flashing
 - PCI slots (tested with CT4810 audio card)
 - fancontrol (Only CPU fan can be regulated)
 - Audio (Rear ports only)

What does not work:
 - Hell knows what might be wrong

What is not tested:
 - PCIe x1
 - IDE
 - Floppy
 - Parallel port

Change-Id: I66b216af740680c390ea82e4fe07737c20227cc6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons 2018-09-18 12:09:23 +02:00 committed by Patrick Georgi
parent 174ca43583
commit 884dfb6d3d
4 changed files with 282 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/asrock/g41c-gs/Kconfig
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@ -14,8 +14,9 @@
# GNU General Public License for more details. # GNU General Public License for more details.
# #
if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS \ if BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41C_GS_R2_0 || \
|| BOARD_ASROCK_G41M_VS3_R2_0 BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_S3 || \
BOARD_ASROCK_G41M_VS3_R2_0
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
@ -25,7 +26,8 @@ config BOARD_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0 select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0
select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \ select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \
|| BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_VS3_R2_0 || BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_S3 \
|| BOARD_ASROCK_G41M_VS3_R2_0
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024 select BOARD_ROMSIZE_KB_1024
select PCIEXP_ASPM select PCIEXP_ASPM
@ -47,6 +49,7 @@ config VARIANT_DIR
default "g41c-gs-r2" if BOARD_ASROCK_G41C_GS_R2_0 default "g41c-gs-r2" if BOARD_ASROCK_G41C_GS_R2_0
default "g41c-gs" if BOARD_ASROCK_G41C_GS default "g41c-gs" if BOARD_ASROCK_G41C_GS
default "g41m-gs" if BOARD_ASROCK_G41M_GS default "g41m-gs" if BOARD_ASROCK_G41M_GS
default "g41m-s3" if BOARD_ASROCK_G41M_S3
default "g41m-vs3-r2" if BOARD_ASROCK_G41M_VS3_R2_0 default "g41m-vs3-r2" if BOARD_ASROCK_G41M_VS3_R2_0
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
@ -54,6 +57,7 @@ config MAINBOARD_PART_NUMBER
default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0 default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0
default "G41C-GS" if BOARD_ASROCK_G41C_GS default "G41C-GS" if BOARD_ASROCK_G41C_GS
default "G41M-GS" if BOARD_ASROCK_G41M_GS default "G41M-GS" if BOARD_ASROCK_G41M_GS
default "G41M-S3" if BOARD_ASROCK_G41M_S3
default "G41M-VS3 R2.0" if BOARD_ASROCK_G41M_VS3_R2_0 default "G41M-VS3 R2.0" if BOARD_ASROCK_G41M_VS3_R2_0
config DEVICETREE config DEVICETREE
@ -61,6 +65,7 @@ config DEVICETREE
default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0 default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS
default "variants/g41m-s3/devicetree.cb" if BOARD_ASROCK_G41M_S3
default "variants/g41m-vs3-r2/devicetree.cb" if BOARD_ASROCK_G41M_VS3_R2_0 default "variants/g41m-vs3-r2/devicetree.cb" if BOARD_ASROCK_G41M_VS3_R2_0
config MAX_CPUS config MAX_CPUS
@ -71,4 +76,4 @@ config MAX_CPUS
config INTEL_GMA_VBT_FILE config INTEL_GMA_VBT_FILE
default "src/mainboard/$(MAINBOARDDIR)/data.vbt" default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
endif # BOARD_ASROCK_G41C_GS_R2_0 endif # BOARD_ASROCK_G41*

3
src/mainboard/asrock/g41c-gs/Kconfig.name
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@ -7,5 +7,8 @@ config BOARD_ASROCK_G41C_GS
config BOARD_ASROCK_G41M_GS config BOARD_ASROCK_G41M_GS
bool "G41M-GS" bool "G41M-GS"
config BOARD_ASROCK_G41M_S3
bool "G41M-S3"
config BOARD_ASROCK_G41M_VS3_R2_0 config BOARD_ASROCK_G41M_VS3_R2_0
bool "G41M-VS3 R2.0" bool "G41M-VS3 R2.0"

148
src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb Normal file
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@ -0,0 +1,148 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30
end
device pci 1.0 on end # PEG
device pci 2.0 on # Integrated graphics controller
subsystemid 0x1849 0x2e32
end
device pci 3.0 off end # ME
device pci 3.1 off end # ME
chip southbridge/intel/i82801gx # Southbridge
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b"
register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440"
device pci 1b.0 on # Audio
subsystemid 0x1849 0x3662
end
device pci 1c.0 on # PCIe 1
subsystemid 0x1849 0x27d0
end
device pci 1c.1 on # PCIe 2
subsystemid 0x1849 0x27d2
end
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 off end # PCIe 5
device pci 1c.5 off end # PCIe 6
device pci 1d.0 on # USB
subsystemid 0x1849 0x27c8
end
device pci 1d.1 on # USB
subsystemid 0x1849 0x27c9
end
device pci 1d.2 on # USB
subsystemid 0x1849 0x27ca
end
device pci 1d.3 on # USB
subsystemid 0x1849 0x27cb
end
device pci 1d.7 on # USB
subsystemid 0x1849 0x27cc
end
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
subsystemid 0x1849 0x27b8
chip superio/winbond/w83627dhg
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel port
# global
irq 0x28 = 0x70
irq 0x2c = 0xd2
# parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # COM2
device pnp 2e.5 on # Keyboard & Mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 0x0c
irq 0xf0 = 0x83
end
device pnp 2e.6 off end # SPI
device pnp 2e.7 off end # GPIO6
device pnp 2e.8 off end # WDT0#, PLED
device pnp 2e.9 on end # GPIO2
device pnp 2e.109 on # GPIO3
irq 0xfe = 0x07
end
device pnp 2e.209 on # GPIO4
irq 0xf4 = 0x74
end
device pnp 2e.309 off end # GPIO5
device pnp 2e.a on # ACPI
irq 0xe4 = 0x10 # Power dram during s3
end
device pnp 2e.b on # HWM, front panel LED
io 0x60 = 0x290
irq 0x70 = 0
end
device pnp 2e.c off end # PECI, SST
end
end
device pci 1f.1 on # PATA/IDE
subsystemid 0x1849 0x27df
end
device pci 1f.2 on # SATA
subsystemid 0x1849 0x27c0
end
device pci 1f.3 on # SMbus
subsystemid 0x1849 0x27da
end
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
end

122
src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c Normal file
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@ -0,0 +1,122 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_GPIO,
.gpio10 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_GPIO,
.gpio26 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_OUTPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_OUTPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_OUTPUT,
.gpio18 = GPIO_DIR_OUTPUT,
.gpio20 = GPIO_DIR_OUTPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_OUTPUT,
.gpio26 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio10 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio16 = GPIO_LEVEL_LOW,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio20 = GPIO_LEVEL_LOW,
.gpio24 = GPIO_LEVEL_HIGH,
.gpio25 = GPIO_LEVEL_LOW,
.gpio26 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
.gpio6 = GPIO_INVERT,
.gpio12 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
.gpio15 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio34 = GPIO_LEVEL_LOW,
.gpio38 = GPIO_LEVEL_HIGH,
.gpio39 = GPIO_LEVEL_LOW,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
};