From 885e8cb36aabc5b7023c9fb4d38c0553b77a7bb0 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 27 Nov 2023 00:15:59 -0500 Subject: [PATCH] sb/intel/bd82x6x: Honor POST code Kconfig option This southbridge can route POST codes written to port 0x80 to either LPC or PCI, but currently always route them to LPC. Change it so that POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is selected, LPC otherwise. Rename the static function because POST codes no longer always go to LPC. Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Nico Huber --- src/southbridge/intel/bd82x6x/bootblock.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7e52..3260021d08 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -5,10 +5,13 @@ #include #include "pch.h" -static void enable_port80_on_lpc(void) +static void setup_port80(void) { - /* Enable port 80 POST on LPC */ - RCBA32(GCS) &= (~0x04); + /* Enable port 80 POST */ + if (CONFIG(POST_DEVICE_PCI_PCIE)) + RCBA32(GCS) |= 0x04; /* ... on PCI(e) */ + else + RCBA32(GCS) &= (~0x04); /* ... on LPC */ } static void set_spi_speed(void) @@ -37,7 +40,7 @@ void bootblock_early_southbridge_init(void) early_pch_init(); - enable_port80_on_lpc(); + setup_port80(); set_spi_speed(); /* Enable upper 128bytes of CMOS */