src: Use tabs for indentation
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
d9169f826a
commit
88607a4b10
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@ -265,7 +265,7 @@ static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_d
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min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
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#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
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/*
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/*
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* Let's record the device of last HT device, so we can set the unitid
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* to CONFIG_HT_CHAIN_END_UNITID_BASE.
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*/
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@ -28,7 +28,7 @@ static void at24rf08c_init(struct device *dev)
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if (!dev->enabled)
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return;
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/* Ensure that EEPROM/RFID chip is not accessible through RFID.
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/* Ensure that EEPROM/RFID chip is not accessible through RFID.
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Need to do it only on 5c. */
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if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c)
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return;
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@ -39,7 +39,7 @@ static int at24rf08c_read_byte(struct device *dev, u8 addr)
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int t = -1;
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int j;
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/* After a register write AT24RF08C (which we issued in init function)
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/* After a register write AT24RF08C (which we issued in init function)
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sometimes stops responding. Retry several times in case of failure.
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*/
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for (j = 0; j < 100; j++) {
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@ -103,7 +103,7 @@ int intel_vga_int15_handler(void)
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}
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break;
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default:
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default:
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printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
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break;
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}
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@ -108,14 +108,14 @@ struct vbios_data {
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#define BDB_SKIP 254 /* VBIOS private block, ignore */
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struct bdb_general_features {
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/* bits 1 */
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/* bits 1 */
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u8 panel_fitting:2;
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u8 flexaim:1;
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u8 msg_enable:1;
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u8 clear_screen:3;
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u8 color_flip:1;
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/* bits 2 */
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/* bits 2 */
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u8 download_ext_vbt:1;
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u8 enable_ssc:1;
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u8 ssc_freq:1;
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@ -125,17 +125,17 @@ struct bdb_general_features {
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u8 display_clock_mode:1;
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u8 rsvd8:1; /* finish byte */
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/* bits 3 */
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/* bits 3 */
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u8 disable_smooth_vision:1;
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u8 single_dvi:1;
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u8 rsvd9:1;
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u8 fdi_rx_polarity_inverted:1;
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u8 rsvd10:4; /* finish byte */
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/* bits 4 */
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/* bits 4 */
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u8 legacy_monitor_detect;
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/* bits 5 */
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/* bits 5 */
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u8 int_crt_support:1;
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u8 int_tv_support:1;
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u8 int_efp_support:1;
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@ -603,7 +603,7 @@ struct bdb_edp {
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#define SWF14_PM_APM_12 (0x2 << 16)
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#define SWF14_PM_APM_11 (0x1 << 16)
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#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
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/* if GR18 indicates a display switch */
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/* if GR18 indicates a display switch */
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#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
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#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
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#define SWF14_DS_PIPEB_TV2_EN (1<<13)
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@ -620,9 +620,9 @@ struct bdb_edp {
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#define SWF14_DS_PIPEA_EFP_EN (1<<2)
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#define SWF14_DS_PIPEA_TV_EN (1<<1)
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#define SWF14_DS_PIPEA_CRT_EN (1<<0)
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/* if GR18 indicates a panel fitting request */
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/* if GR18 indicates a panel fitting request */
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#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
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/* if GR18 indicates an APM change request */
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/* if GR18 indicates an APM change request */
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#define SWF14_APM_HIBERNATE 0x4
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#define SWF14_APM_SUSPEND 0x3
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#define SWF14_APM_STANDBY 0x1
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@ -265,7 +265,7 @@ static void wifi_pci_dev_init(struct device *dev)
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val = pci_read_config16(dev, PMCS_DR);
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if (val & PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0);
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}
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}
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}
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static struct pci_operations pci_ops = {
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@ -34,8 +34,8 @@ enum { /* export_type */
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/* Callback for decodeVpdString to invoke. */
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typedef int VpdDecodeCallback(const uint8_t *key, int32_t key_len,
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const uint8_t *value, int32_t value_len,
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void *arg);
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const uint8_t *value, int32_t value_len,
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void *arg);
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/* Container data types */
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struct StringPair {
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@ -153,53 +153,53 @@ int decodeVpdString(
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void initContainer(struct PairContainer *container);
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struct StringPair *findString(struct PairContainer *container,
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const uint8_t *key,
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struct StringPair ***prev_next);
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const uint8_t *key,
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struct StringPair ***prev_next);
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/* If key is already existed in container, its value will be replaced.
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* If not existed, creates new entry in container.
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*/
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void setString(struct PairContainer *container,
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const uint8_t *key,
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const uint8_t *value,
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const int pad_len);
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const uint8_t *key,
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const uint8_t *value,
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const int pad_len);
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/* merge all entries in src into dst. If key is duplicate, overwrite it.
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*/
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void mergeContainer(struct PairContainer *dst,
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const struct PairContainer *src);
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const struct PairContainer *src);
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/* subtract src from dst.
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*/
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int subtractContainer(struct PairContainer *dst,
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const struct PairContainer *src);
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const struct PairContainer *src);
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/* Given a container, encode its all entries into the buffer.
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*/
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int encodeContainer(const struct PairContainer *container,
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const int max_buf_len,
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uint8_t *buf,
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int *generated);
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const int max_buf_len,
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uint8_t *buf,
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int *generated);
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/* Given a VPD blob, decode its entries and push into container.
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*/
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int decodeToContainer(struct PairContainer *container,
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const int32_t max_len,
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const uint8_t *input_buf,
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int32_t *consumed);
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const int32_t max_len,
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const uint8_t *input_buf,
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int32_t *consumed);
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/* Set filter for exporting functions.
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* If filter is NULL, resets the filter so that everything can be exported.
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*/
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int setContainerFilter(struct PairContainer *container,
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const uint8_t *filter);
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const uint8_t *filter);
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/*
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* Remove a key.
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* Returns VPD_OK if deleted successfully. Otherwise, VPD_FAIL.
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*/
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int deleteKey(struct PairContainer *container,
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const uint8_t *key);
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const uint8_t *key);
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/*
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* Returns number of pairs in container.
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@ -216,10 +216,10 @@ int lenOfContainer(const struct PairContainer *container);
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* generated.
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*/
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int exportContainer(const int export_type,
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const struct PairContainer *container,
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const int max_buf_len,
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uint8_t *buf,
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int *generated);
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const struct PairContainer *container,
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const int max_buf_len,
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uint8_t *buf,
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int *generated);
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void destroyContainer(struct PairContainer *container);
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@ -146,12 +146,12 @@ Device (EC0)
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{
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Store ("-----> EC: _Q43", Debug)
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Store (BRIG, Local0)
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Increment (Local0)
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If (LGreater (Local0, 0xAA)) {
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Store (BRIG, Local0)
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Increment (Local0)
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If (LGreater (Local0, 0xAA)) {
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Store (0xAA, Local0)
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}
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Store (Local0, BRIG)
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}
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Store (Local0, BRIG)
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\_SB.PCI0.GFX0.INCB ()
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@ -162,13 +162,13 @@ Device (EC0)
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{
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Store ("-----> EC: _Q44", Debug)
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Store (BRIG, Local0)
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Decrement (Local0)
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If (LLess (Local0, 0xA0))
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{
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Store (BRIG, Local0)
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Decrement (Local0)
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If (LLess (Local0, 0xA0))
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{
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Store (0xA0, Local0)
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}
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Store (Local0, BRIG)
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}
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Store (Local0, BRIG)
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\_SB.PCI0.GFX0.DECB ()
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@ -193,7 +193,7 @@ Device (EC0)
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} Else {
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Return (Zero)
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}
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}
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}
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Method (_ON) {
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If (FCOS) {
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Store (One, FSL4)
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@ -26,7 +26,7 @@
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#include <include/device/pci_def.h>
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u32 Get_NB32(u32 dev, u32 reg)
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{
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return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
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return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
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}
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#endif
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@ -43,7 +43,7 @@ struct db_limit {
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static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
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{
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struct db_limit limit;
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struct db_limit limit;
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switch (s->selected_timings.mem_clk) {
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default:
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@ -209,7 +209,7 @@ static void vx900_lpc_read_resources(struct device *dev)
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static void vx900_lpc_set_resources(struct device *dev)
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{
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struct resource *mmio, *spi;
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u32 reg;
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u32 reg;
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mmio = find_resource(dev, VX900_MMCONFIG_MBAR);
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if (mmio) {
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@ -58,5 +58,5 @@ static void bootblock_mmu_init(void)
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C0_ENTRYLO_COHERENCY_WB));
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assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB));
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assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size,
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C0_ENTRYLO_COHERENCY_UC));
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C0_ENTRYLO_COHERENCY_UC));
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}
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@ -174,7 +174,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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return;
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}
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cfg = dev->chip_info;
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cfg = dev->chip_info;
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if(cfg->lpss_s0ix_enable)
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fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
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@ -573,7 +573,7 @@ static void glk_fsp_silicon_init_params_cb(
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void __weak mainboard_devtree_update(struct device *dev)
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{
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/* Override dev tree settings per board */
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/* Override dev tree settings per board */
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}
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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@ -260,7 +260,7 @@ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink)
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int nhlt_soc_add_rt5682(struct nhlt *nhlt, int hwlink)
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{
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/* Virtual bus id of SSP links are the hardware port ids proper. */
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return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors,
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ARRAY_SIZE(rt5682_descriptors));
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/* Virtual bus id of SSP links are the hardware port ids proper. */
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return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors,
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ARRAY_SIZE(rt5682_descriptors));
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}
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@ -170,7 +170,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
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}
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static void setup_gpio_route(const struct soc_gpio_map *sus,
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const struct soc_gpio_map *core)
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const struct soc_gpio_map *core)
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{
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uint32_t route_reg = 0;
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int i;
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@ -52,7 +52,7 @@ uint16_t get_pmbase(void)
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}
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static void print_num_status_bits(int num_bits, uint32_t status,
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const char *bit_names[])
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const char *bit_names[])
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{
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int i;
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@ -97,8 +97,8 @@ static void spi_init(void)
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}
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/* Entry from cache-as-ram.inc. */
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void *asmlinkage romstage_main(unsigned long bist,
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uint32_t tsc_low, uint32_t tsc_hi)
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void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
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uint32_t tsc_hi)
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{
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struct romstage_params rp = {
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.bist = bist,
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@ -17,6 +17,6 @@
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void *cbmem_top(void)
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{
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/* not implemented yet */
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/* not implemented yet */
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return (void *) NULL;
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}
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@ -231,7 +231,7 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = {
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.did = NHLT_DID_SSP,
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.formats = max98373_capture_formats,
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.num_formats = ARRAY_SIZE(max98373_capture_formats),
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},
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},
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};
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int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels)
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@ -155,8 +155,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
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if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
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dpr_size = sa_get_dpr_size();
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/* Get SoC reserve memory size as per user selection */
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reserved_mmio_size = soc_reserved_mmio_size();
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/* Get SoC reserve memory size as per user selection */
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reserved_mmio_size = soc_reserved_mmio_size();
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top_of_ram = (uintptr_t)cbmem_top();
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@ -186,7 +186,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
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}
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static void setup_gpio_route(const struct soc_gpio_map *sus,
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const struct soc_gpio_map *core)
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const struct soc_gpio_map *core)
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{
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uint32_t route_reg = 0;
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int i;
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@ -319,7 +319,7 @@ void write_ssus_gpio(uint8_t gpio_num, uint8_t val)
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* pad value: PAD_VAL_HIGH / PAD_VAL_LOW
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*/
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static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
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uint32_t pconf0, uint32_t pad_val)
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uint32_t pconf0, uint32_t pad_val)
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{
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uint32_t reg;
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uint32_t *pad_addr;
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@ -266,34 +266,34 @@ Device (TSR1)
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#ifdef DPTF_ENABLE_FAN_CONTROL
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#ifdef DPTF_TSR1_ACTIVE_AC0
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Method (_AC0)
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{
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Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
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}
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Method (_AC0)
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{
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Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
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}
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#endif
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#ifdef DPTF_TSR1_ACTIVE_AC1
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Method (_AC1)
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{
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Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
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}
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Method (_AC1)
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{
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Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
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}
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#endif
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#ifdef DPTF_TSR1_ACTIVE_AC2
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Method (_AC2)
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{
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Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
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}
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Method (_AC2)
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{
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Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
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}
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#endif
|
||||
#ifdef DPTF_TSR1_ACTIVE_AC3
|
||||
Method (_AC3)
|
||||
{
|
||||
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
|
||||
}
|
||||
Method (_AC3)
|
||||
{
|
||||
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
|
||||
}
|
||||
#endif
|
||||
#ifdef DPTF_TSR1_ACTIVE_AC4
|
||||
Method (_AC4)
|
||||
{
|
||||
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
|
||||
}
|
||||
Method (_AC4)
|
||||
{
|
||||
Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -195,8 +195,8 @@ Device (XHCI)
|
|||
Store (3, ^UPSW)
|
||||
|
||||
/* Enable d3hot and SS link trunk clock gating */
|
||||
Store(One, ^D3HE)
|
||||
Store(One, ^STGE)
|
||||
Store(One, ^D3HE)
|
||||
Store(One, ^STGE)
|
||||
|
||||
/* Now put device in D3 */
|
||||
Store (3, Local0)
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = {
|
|||
.did = NHLT_DID_SSP,
|
||||
.formats = max98373_capture_formats,
|
||||
.num_formats = ARRAY_SIZE(max98373_capture_formats),
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
int nhlt_soc_add_max98373(struct nhlt *nhlt, int hwlink)
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ inline u8 is_dual_rank(u32 channel,
|
|||
const struct mt8173_sdram_params *sdram_params)
|
||||
{
|
||||
/* judge ranks from EMI_CONA[17] (cha) and EMI_CONA[16] (chb) */
|
||||
return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0;
|
||||
return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0;
|
||||
}
|
||||
|
||||
static void mem_pll_pre_init(u32 channel)
|
||||
|
|
|
|||
|
|
@ -343,7 +343,7 @@ static u8 dqs_gw_coarse_tune_calib(u32 channel, u8 coarse_val)
|
|||
gw_ret[i] = dqs_gw_test(channel);
|
||||
/* judge test result */
|
||||
if (gw_ret[i] != 0)
|
||||
return opt_coarse_val[i];
|
||||
return opt_coarse_val[i];
|
||||
}
|
||||
|
||||
/* abnormal test result, set to default coarse tune value */
|
||||
|
|
@ -747,7 +747,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank,
|
|||
}
|
||||
|
||||
/* Default dle value is set when test error (error recovery).
|
||||
* Others, adjusted dle calibration value is set normally.
|
||||
* Others, adjusted dle calibration value is set normally.
|
||||
*/
|
||||
set_dle_factor(channel, best_step);
|
||||
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ static void mt6391_configure_vcama(enum ldo_voltage vsel)
|
|||
mt6391_write(PMIC_RG_ANALDO_CON6, vsel - 2, PMIC_RG_VCAMA_VOSEL_MASK,
|
||||
PMIC_RG_VCAMA_VOSEL_SHIFT);
|
||||
mt6391_write(PMIC_RG_ANALDO_CON2, 1, PMIC_RG_VCAMA_EN_MASK,
|
||||
PMIC_RG_VCAMA_EN_SHIFT);
|
||||
PMIC_RG_VCAMA_EN_SHIFT);
|
||||
}
|
||||
|
||||
void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
|
||||
|
|
|
|||
|
|
@ -212,7 +212,7 @@ void i2c_init(unsigned bus)
|
|||
struct tegra_i2c_regs *regs;
|
||||
|
||||
if (bus >= g_num_i2c_buses) {
|
||||
printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
|
||||
printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
|
||||
bus);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ struct soc_nvidia_tegra124_config {
|
|||
|
||||
int hpd_unplug_min_us;
|
||||
int hpd_plug_min_us;
|
||||
int hpd_irq_min_us;
|
||||
int hpd_irq_min_us;
|
||||
|
||||
int href_to_sync;
|
||||
int hsync_width;
|
||||
|
|
|
|||
|
|
@ -40,26 +40,26 @@ struct tegra_dc dc_data;
|
|||
int dump = 0;
|
||||
unsigned long READL(void *p)
|
||||
{
|
||||
unsigned long value;
|
||||
unsigned long value;
|
||||
|
||||
/*
|
||||
* In case of hard hung on readl(p), we can set dump > 1 to print out
|
||||
* the address accessed.
|
||||
*/
|
||||
if (dump > 1)
|
||||
if (dump > 1)
|
||||
printk(BIOS_SPEW, "readl %p\n", p);
|
||||
|
||||
value = read32(p);
|
||||
if (dump)
|
||||
value = read32(p);
|
||||
if (dump)
|
||||
printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
|
||||
return value;
|
||||
return value;
|
||||
}
|
||||
|
||||
void WRITEL(unsigned long value, void *p)
|
||||
{
|
||||
if (dump)
|
||||
if (dump)
|
||||
printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
|
||||
write32(p, value);
|
||||
write32(p, value);
|
||||
}
|
||||
|
||||
/* return in 1000ths of a Hertz */
|
||||
|
|
|
|||
|
|
@ -1362,10 +1362,10 @@ void dp_init(void *_config)
|
|||
struct tegra_dc *dc = config->dc_data;
|
||||
struct tegra_dc_dp_data *dp = &dp_data;
|
||||
|
||||
// set up links among config, dc, dp and sor
|
||||
dp->dc = dc;
|
||||
dc->out = dp;
|
||||
dp->sor.dc = dc;
|
||||
// set up links among config, dc, dp and sor
|
||||
dp->dc = dc;
|
||||
dc->out = dp;
|
||||
dp->sor.dc = dc;
|
||||
|
||||
dp->sor.power_is_up = 0;
|
||||
dp->sor.base = (void *)TEGRA_ARM_SOR;
|
||||
|
|
@ -1427,7 +1427,7 @@ void dp_enable(void *_dp)
|
|||
if (tegra_dc_dp_init_max_link_cfg(config, dp, &dp->link_cfg)) {
|
||||
printk(BIOS_ERR, "dp: failed to init link configuration\n");
|
||||
goto error_enable;
|
||||
}
|
||||
}
|
||||
|
||||
tegra_dc_sor_enable_dp(&dp->sor);
|
||||
|
||||
|
|
|
|||
|
|
@ -25,26 +25,26 @@
|
|||
int dump = 0;
|
||||
unsigned long READL(void *p)
|
||||
{
|
||||
unsigned long value;
|
||||
unsigned long value;
|
||||
|
||||
/*
|
||||
* In case of hard hung on readl(p), we can set dump > 1 to print out
|
||||
* the address accessed.
|
||||
*/
|
||||
if (dump > 1)
|
||||
if (dump > 1)
|
||||
printk(BIOS_SPEW, "readl %p\n", p);
|
||||
|
||||
value = read32(p);
|
||||
if (dump)
|
||||
value = read32(p);
|
||||
if (dump)
|
||||
printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
|
||||
return value;
|
||||
return value;
|
||||
}
|
||||
|
||||
void WRITEL(unsigned long value, void *p)
|
||||
{
|
||||
if (dump)
|
||||
if (dump)
|
||||
printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
|
||||
write32(p, value);
|
||||
write32(p, value);
|
||||
}
|
||||
|
||||
/* return in 1000ths of a Hertz */
|
||||
|
|
@ -76,7 +76,7 @@ static void print_mode(const struct soc_nvidia_tegra210_config *config)
|
|||
}
|
||||
|
||||
int update_display_mode(struct display_controller *disp_ctrl,
|
||||
struct soc_nvidia_tegra210_config *config)
|
||||
struct soc_nvidia_tegra210_config *config)
|
||||
{
|
||||
print_mode(config);
|
||||
|
||||
|
|
@ -124,7 +124,7 @@ int update_display_mode(struct display_controller *disp_ctrl,
|
|||
}
|
||||
|
||||
void update_display_shift_clock_divider(struct display_controller *disp_ctrl,
|
||||
u32 shift_clock_div)
|
||||
u32 shift_clock_div)
|
||||
{
|
||||
WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
|
||||
(shift_clock_div & 0xff) << SHIFT_CLK_DIVIDER_SHIFT,
|
||||
|
|
|
|||
|
|
@ -886,12 +886,12 @@ static int dsi_probe_if(int dsi_index,
|
|||
/*
|
||||
* Set default value. Will be taken from attached device once detected
|
||||
*/
|
||||
dsi->flags = 0;
|
||||
dsi->format = MIPI_DSI_FMT_RGB888;
|
||||
dsi->lanes = 4;
|
||||
dsi->flags = 0;
|
||||
dsi->format = MIPI_DSI_FMT_RGB888;
|
||||
dsi->lanes = 4;
|
||||
|
||||
/* get tegra_mipi_device */
|
||||
dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index);
|
||||
dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index);
|
||||
|
||||
/* calibrate */
|
||||
err = tegra_dsi_pad_calibrate(dsi);
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#include <arch/asm.h>
|
||||
#include "stack.S"
|
||||
|
||||
.section ".text", "ax", %progbits
|
||||
.section ".text", "ax", %progbits
|
||||
|
||||
ENTRY(main)
|
||||
stack_init stack_top=_estack stack_bottom=_stack seed=0 func=romstage
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
* @func : Function to call after initializing stack
|
||||
*/
|
||||
.macro stack_init stack_top, stack_bottom, seed, func
|
||||
/* Check if stack seeding is required */
|
||||
/* Check if stack seeding is required */
|
||||
mov r0, #\seed
|
||||
cmp r0, #1
|
||||
bne call_func
|
||||
|
|
|
|||
|
|
@ -657,7 +657,7 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
|
|||
|| ((bus == BLSP1_SPI) && (cs > 0))) {
|
||||
printk(BIOS_ERR,
|
||||
"SPI error: unsupported bus %d (Supported busses 0, 1 and 2) "
|
||||
"or chipselect\n", bus);
|
||||
"or chipselect\n", bus);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -63,17 +63,17 @@ void gpio_tlmm_config_set(gpio_t gpio, unsigned func,
|
|||
unsigned pull, unsigned drvstr,
|
||||
unsigned enable)
|
||||
{
|
||||
unsigned val = 0;
|
||||
unsigned val = 0;
|
||||
|
||||
if (gpio_not_valid(gpio))
|
||||
return;
|
||||
|
||||
val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT;
|
||||
val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT;
|
||||
val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT;
|
||||
val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT;
|
||||
val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT;
|
||||
val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT;
|
||||
val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT;
|
||||
val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT;
|
||||
|
||||
write32(GPIO_CONFIG_ADDR(gpio), val);
|
||||
write32(GPIO_CONFIG_ADDR(gpio), val);
|
||||
}
|
||||
|
||||
/*******************************************************
|
||||
|
|
@ -93,8 +93,8 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned *func,
|
|||
unsigned *pull, unsigned *drvstr,
|
||||
unsigned *enable)
|
||||
{
|
||||
unsigned val;
|
||||
void *addr = GPIO_CONFIG_ADDR(gpio);
|
||||
unsigned val;
|
||||
void *addr = GPIO_CONFIG_ADDR(gpio);
|
||||
|
||||
if (gpio_not_valid(gpio))
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ void system_clock_init(void)
|
|||
write32(&exynos_clock->ipll_lock, IPLL_LOCK_VAL);
|
||||
write32(&exynos_clock->spll_lock, SPLL_LOCK_VAL);
|
||||
write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL);
|
||||
write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
|
||||
write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL);
|
||||
|
||||
setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
|
||||
|
||||
|
|
@ -138,7 +138,7 @@ void system_clock_init(void)
|
|||
while ((read32(&exynos_clock->spll_con0) & PLL_LOCKED) == 0)
|
||||
;
|
||||
|
||||
/* We use RPLL as the source for FIMD video stream clock */
|
||||
/* We use RPLL as the source for FIMD video stream clock */
|
||||
write32(&exynos_clock->rpll_con1, RPLL_CON1_VAL);
|
||||
write32(&exynos_clock->rpll_con2, RPLL_CON2_VAL);
|
||||
/* computed by gabe from first principles; u-boot is probably
|
||||
|
|
|
|||
|
|
@ -304,16 +304,16 @@ void exynos_fimd_window_off(unsigned int win_id)
|
|||
|
||||
static void exynos5_set_system_display(void)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
unsigned int cfg = 0;
|
||||
|
||||
/*
|
||||
* system register path set
|
||||
* 0: MIE/MDNIE
|
||||
* 1: FIMD Bypass
|
||||
*/
|
||||
cfg = lreadl(&exynos_sysreg->disp1blk_cfg);
|
||||
cfg |= (1 << 15);
|
||||
lwritel(cfg, &exynos_sysreg->disp1blk_cfg);
|
||||
/*
|
||||
* system register path set
|
||||
* 0: MIE/MDNIE
|
||||
* 1: FIMD Bypass
|
||||
*/
|
||||
cfg = lreadl(&exynos_sysreg->disp1blk_cfg);
|
||||
cfg |= (1 << 15);
|
||||
lwritel(cfg, &exynos_sysreg->disp1blk_cfg);
|
||||
}
|
||||
|
||||
void exynos_fimd_lcd_init(vidinfo_t *vid)
|
||||
|
|
|
|||
|
|
@ -48,6 +48,6 @@ Method(TRAP, 1, Serialized)
|
|||
|
||||
Method(_PIC, 1)
|
||||
{
|
||||
// Remember the OS' IRQ routing choice.
|
||||
Store(Arg0, PICM)
|
||||
// Remember the OS' IRQ routing choice.
|
||||
Store(Arg0, PICM)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ Device (EHC1)
|
|||
Store (Arg0, VISI)
|
||||
|
||||
Return (PCKG)
|
||||
}
|
||||
}
|
||||
|
||||
// How many are there?
|
||||
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
|
||||
|
|
@ -112,7 +112,7 @@ Device (EHC2)
|
|||
Store (Arg0, VISI)
|
||||
|
||||
Return (PCKG)
|
||||
}
|
||||
}
|
||||
|
||||
// How many are there?
|
||||
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ void pch_enable_lpc(void)
|
|||
}
|
||||
|
||||
int early_pch_init(const void *gpio_map,
|
||||
const struct rcba_config_instruction *rcba_config)
|
||||
const struct rcba_config_instruction *rcba_config)
|
||||
{
|
||||
int wake_from_s3;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue