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soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16 

Change-Id: I97c73324900a0677165afa3f5b182a336d534968
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
This commit is contained in:
Felix Held 2021-01-19 23:51:45 +01:00
parent eb723f01af
commit 88615629c0
2 changed files with 5 additions and 0 deletions
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4
src/soc/amd/cezanne/Kconfig
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@ -108,6 +108,10 @@ config MMCONF_BUS_NUMBER
int int
default 64 default 64
config MAX_CPUS
int
default 16
config CONSOLE_UART_BASE_ADDRESS config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
hex hex

1
src/soc/amd/cezanne/Makefile.inc
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@ -2,6 +2,7 @@
ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/mtrr
# Beware that all-y also adds the compilation unit to verstage on PSP # Beware that all-y also adds the compilation unit to verstage on PSP