soc/intel/common: Add option to pass SoC IO resource
This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* Copyright (C) 2017-2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -82,7 +82,7 @@ void lpc_configure_pads(void)
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gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
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}
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void lpc_init(struct device *dev)
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void lpc_soc_init(struct device *dev)
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{
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const struct soc_intel_apollolake_config *cfg;
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -181,7 +181,7 @@ static void clock_gate_8254(const struct device *dev)
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itss_clock_gate_8254();
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}
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void lpc_init(struct device *dev)
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void lpc_soc_init(struct device *dev)
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{
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/* Legacy initialization */
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isa_dma_init();
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* Copyright (C) 2017-2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -71,7 +71,9 @@ void lpc_open_mmio_window(uintptr_t base, size_t size);
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bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
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/* Init SoC Spcific LPC features. Common definition will be weak and
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each soc will need to define the init. */
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void lpc_init(struct device *dev);
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void lpc_soc_init(struct device *dev);
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/* Fill up LPC IO resource structure inside SoC directory */
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void pch_lpc_soc_fill_io_resources(struct device *dev);
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/* Init LPC GPIO pads */
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void lpc_configure_pads(void);
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/* Get SoC speicific MMIO ranges */
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@ -102,5 +104,8 @@ void soc_get_gen_io_dec_range(const struct device *dev,
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uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
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/* Mirror generic IO decoder range register settings into DMI PCR. */
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void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
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/* Add resource into LPC PCI device space */
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void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
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uintptr_t base, size_t size, unsigned long flags);
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#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* Copyright (C) 2017-2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,32 +21,52 @@
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#include <intelblocks/lpc_lib.h>
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#include <soc/pm.h>
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/* SoC overrides */
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/* Common weak definition, needs to be implemented in each soc LPC driver. */
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__attribute__((weak)) void lpc_init(struct device *dev) { /* no-op */ }
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static void soc_lpc_add_io_resources(device_t dev)
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__attribute__((weak)) void lpc_soc_init(struct device *dev)
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{
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struct resource *res;
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/* Add the default claimed legacy IO range for the LPC device. */
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res = new_resource(dev, 0);
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res->base = 0;
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res->size = 0x1000;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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/* no-op */
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}
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static void soc_lpc_read_resources(device_t dev)
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/* Fill up LPC IO resource structure inside SoC directory */
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__attribute__((weak)) void pch_lpc_soc_fill_io_resources(struct device *dev)
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{
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/* no-op */
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}
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void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
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uintptr_t base, size_t size, unsigned long flags)
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{
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struct resource *res;
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res = new_resource(dev, offset);
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res->base = base;
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res->size = size;
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res->flags = flags;
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}
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static void pch_lpc_add_io_resources(device_t dev)
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{
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/* Add the default claimed legacy IO range for the LPC device. */
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pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
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/* SoC IO resource overrides */
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pch_lpc_soc_fill_io_resources(dev);
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}
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static void pch_lpc_read_resources(device_t dev)
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{
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/* Get the PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add IO resources to LPC. */
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soc_lpc_add_io_resources(dev);
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pch_lpc_add_io_resources(dev);
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}
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static void set_child_resources(struct device *dev);
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static void pch_lpc_set_child_resources(struct device *dev);
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static void loop_resources(struct device *dev)
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static void pch_lpc_loop_resources(struct device *dev)
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{
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struct resource *res;
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@ -62,39 +82,39 @@ static void loop_resources(struct device *dev)
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lpc_open_mmio_window(res->base, res->size);
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}
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}
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set_child_resources(dev);
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pch_lpc_set_child_resources(dev);
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}
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/*
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* Loop through all the child devices' resources, and open up windows to the
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* LPC bus, as appropriate.
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*/
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static void set_child_resources(struct device *dev)
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static void pch_lpc_set_child_resources(struct device *dev)
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{
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struct bus *link;
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struct device *child;
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for (link = dev->link_list; link; link = link->next) {
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for (child = link->children; child; child = child->sibling)
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loop_resources(child);
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pch_lpc_loop_resources(child);
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}
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}
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static void set_resources(device_t dev)
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static void pch_lpc_set_resources(device_t dev)
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{
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pci_dev_set_resources(dev);
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/* Now open up windows to devices which have declared resources. */
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set_child_resources(dev);
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pch_lpc_set_child_resources(dev);
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}
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static struct device_operations device_ops = {
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.read_resources = soc_lpc_read_resources,
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.set_resources = set_resources,
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.read_resources = pch_lpc_read_resources,
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.set_resources = pch_lpc_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.write_acpi_tables = southbridge_write_acpi_tables,
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.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
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.init = lpc_init,
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.init = lpc_soc_init,
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.scan_bus = scan_lpc_bus,
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.ops_pci = &pci_dev_ops_pci,
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};
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@ -122,7 +142,7 @@ static const unsigned short pci_device_ids[] = {
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0
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};
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static const struct pci_driver soc_lpc __pci_driver = {
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static const struct pci_driver pch_lpc __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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0
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};
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static const struct pci_driver pch_lpc __pci_driver = {
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static const struct pci_driver pch_pmc __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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* Copyright (C) 2015-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -115,7 +115,7 @@ static void clock_gate_8254(struct device *dev)
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itss_clock_gate_8254();
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}
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void lpc_init(struct device *dev)
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void lpc_soc_init(struct device *dev)
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{
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/* Legacy initialization */
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isa_dma_init();
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