soc/intel/common: Add option to pass SoC IO resource

This patch ensures common block has option to reserve IO resources
based on SOC requirements. Also add pch_lpc_ prefix to maintain
same function nomenclature across all intel common block.

Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2018-01-10 10:51:50 +05:30
parent 7410f8be8f
commit 888520622b
6 changed files with 59 additions and 34 deletions

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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
* Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -82,7 +82,7 @@ void lpc_configure_pads(void)
gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
}
void lpc_init(struct device *dev)
void lpc_soc_init(struct device *dev)
{
const struct soc_intel_apollolake_config *cfg;

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@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -181,7 +181,7 @@ static void clock_gate_8254(const struct device *dev)
itss_clock_gate_8254();
}
void lpc_init(struct device *dev)
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
isa_dma_init();

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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
* Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -71,7 +71,9 @@ void lpc_open_mmio_window(uintptr_t base, size_t size);
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
/* Init SoC Spcific LPC features. Common definition will be weak and
each soc will need to define the init. */
void lpc_init(struct device *dev);
void lpc_soc_init(struct device *dev);
/* Fill up LPC IO resource structure inside SoC directory */
void pch_lpc_soc_fill_io_resources(struct device *dev);
/* Init LPC GPIO pads */
void lpc_configure_pads(void);
/* Get SoC speicific MMIO ranges */
@ -102,5 +104,8 @@ void soc_get_gen_io_dec_range(const struct device *dev,
uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
/* Mirror generic IO decoder range register settings into DMI PCR. */
void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
/* Add resource into LPC PCI device space */
void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
uintptr_t base, size_t size, unsigned long flags);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */

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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
* Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -21,32 +21,52 @@
#include <intelblocks/lpc_lib.h>
#include <soc/pm.h>
/* SoC overrides */
/* Common weak definition, needs to be implemented in each soc LPC driver. */
__attribute__((weak)) void lpc_init(struct device *dev) { /* no-op */ }
static void soc_lpc_add_io_resources(device_t dev)
__attribute__((weak)) void lpc_soc_init(struct device *dev)
{
struct resource *res;
/* Add the default claimed legacy IO range for the LPC device. */
res = new_resource(dev, 0);
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* no-op */
}
static void soc_lpc_read_resources(device_t dev)
/* Fill up LPC IO resource structure inside SoC directory */
__attribute__((weak)) void pch_lpc_soc_fill_io_resources(struct device *dev)
{
/* no-op */
}
void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
uintptr_t base, size_t size, unsigned long flags)
{
struct resource *res;
res = new_resource(dev, offset);
res->base = base;
res->size = size;
res->flags = flags;
}
static void pch_lpc_add_io_resources(device_t dev)
{
/* Add the default claimed legacy IO range for the LPC device. */
pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
/* SoC IO resource overrides */
pch_lpc_soc_fill_io_resources(dev);
}
static void pch_lpc_read_resources(device_t dev)
{
/* Get the PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add IO resources to LPC. */
soc_lpc_add_io_resources(dev);
pch_lpc_add_io_resources(dev);
}
static void set_child_resources(struct device *dev);
static void pch_lpc_set_child_resources(struct device *dev);
static void loop_resources(struct device *dev)
static void pch_lpc_loop_resources(struct device *dev)
{
struct resource *res;
@ -62,39 +82,39 @@ static void loop_resources(struct device *dev)
lpc_open_mmio_window(res->base, res->size);
}
}
set_child_resources(dev);
pch_lpc_set_child_resources(dev);
}
/*
* Loop through all the child devices' resources, and open up windows to the
* LPC bus, as appropriate.
*/
static void set_child_resources(struct device *dev)
static void pch_lpc_set_child_resources(struct device *dev)
{
struct bus *link;
struct device *child;
for (link = dev->link_list; link; link = link->next) {
for (child = link->children; child; child = child->sibling)
loop_resources(child);
pch_lpc_loop_resources(child);
}
}
static void set_resources(device_t dev)
static void pch_lpc_set_resources(device_t dev)
{
pci_dev_set_resources(dev);
/* Now open up windows to devices which have declared resources. */
set_child_resources(dev);
pch_lpc_set_child_resources(dev);
}
static struct device_operations device_ops = {
.read_resources = soc_lpc_read_resources,
.set_resources = set_resources,
.read_resources = pch_lpc_read_resources,
.set_resources = pch_lpc_set_resources,
.enable_resources = pci_dev_enable_resources,
.write_acpi_tables = southbridge_write_acpi_tables,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.init = lpc_init,
.init = lpc_soc_init,
.scan_bus = scan_lpc_bus,
.ops_pci = &pci_dev_ops_pci,
};
@ -122,7 +142,7 @@ static const unsigned short pci_device_ids[] = {
0
};
static const struct pci_driver soc_lpc __pci_driver = {
static const struct pci_driver pch_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,

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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -111,7 +111,7 @@ static const unsigned short pci_device_ids[] = {
0
};
static const struct pci_driver pch_lpc __pci_driver = {
static const struct pci_driver pch_pmc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,

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@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -115,7 +115,7 @@ static void clock_gate_8254(struct device *dev)
itss_clock_gate_8254();
}
void lpc_init(struct device *dev)
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
isa_dma_init();