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soc/intel/apl: Configure LPC serial IRQ mode 

Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.

TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
     works correctly now, but was confused by the wrong settings before
     because the FSP defaults allowed to disable the LPC clock.

Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Nico Huber 2018-11-27 15:13:22 +01:00 committed by Werner Zeh
parent aaced4a932
commit 8885529e15
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/apollolake/chip.c
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@ -609,6 +609,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,
sizeof(silconfig->PcieRpHotPlug)); sizeof(silconfig->PcieRpHotPlug));
switch (cfg->serirq_mode) {
case SERIRQ_QUIET:
silconfig->SirqEnable = 1;
silconfig->SirqMode = 0;
break;
case SERIRQ_CONTINUOUS:
silconfig->SirqEnable = 1;
silconfig->SirqMode = 1;
break;
case SERIRQ_OFF:
default:
silconfig->SirqEnable = 0;
break;
}
if (cfg->emmc_tx_cmd_cntl != 0) if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
if (cfg->emmc_tx_data_cntl1 != 0) if (cfg->emmc_tx_data_cntl1 != 0)