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mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM 

1. Add a separate devicetree file for soraka variant and add H1 node.
2. Enable H1 TPM for soraka.

BUG=b:36265511

Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19519
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
This commit is contained in:
Furquan Shaikh 2017-05-01 14:23:37 -07:00 committed by Furquan Shaikh
parent d271afc0a7
commit 8888072230
2 changed files with 434 additions and 0 deletions
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2
src/mainboard/google/poppy/Kconfig
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@ -14,12 +14,14 @@ config BOARD_GOOGLE_BASEBOARD_POPPY
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_FSP2_0
select NO_FADT_8042
select POPPY_USE_I2C_TPM if BOARD_GOOGLE_SORAKA
select SOC_INTEL_KABYLAKE
if BOARD_GOOGLE_BASEBOARD_POPPY
config DEVICETREE
string
default "variants/soraka/devicetree.cb" if BOARD_GOOGLE_SORAKA
default "variants/baseboard/devicetree.cb"
config DRIVER_TPM_I2C_BUS

432
src/mainboard/google/poppy/variants/soraka/devicetree.cb Normal file
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@ -0,0 +1,432 @@
chip soc/intel/skylake
# Deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "1"
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "GPP_B"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "IshEnable" = "0"
register "PttSwitch" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "SendVrMbxCmd" = "1" # IMVP8 workaround
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
register "pirqc_routing" = "PCH_IRQ11"
register "pirqd_routing" = "PCH_IRQ11"
register "pirqe_routing" = "PCH_IRQ11"
register "pirqf_routing" = "PCH_IRQ11"
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 4A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 7A | 34A | 35A | 35A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(4),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
}"
# Enable Root port 1.
register "PcieRpEnable[0]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # H1
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
}"
# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
# for TPM communication before memory is up.
register "i2c[1]" = "{
.early_init = 1,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoPci,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
register "speed_shift_enable" = "1"
register "tdp_pl2_override" = "7"
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_E15"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ATML0001""
register "desc" = ""Atmel Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
register "probed" = "1"
device i2c 4b on end
end
end # I2C #0
device pci 15.1 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
device i2c 50 on end
end
end # I2C #1
device pci 15.2 on
chip drivers/intel/mipi_camera
register "acpi_hid" = ""INT3472""
register "acpi_name" = ""PMIC""
register "chip_name" = ""TPS68470 PMIC""
register "device_type" = "INTEL_ACPI_CAMERA_PMIC"
device i2c 4d on end
end
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTID850""
register "acpi_name" = ""CAM0""
register "chip_name" = ""OV 13850 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
# Camera SSDB buffer
register "ssdb.sensor_card_sku" = "0x50"
register "ssdb.link_used" = "0x00"
register "ssdb.lanes_used" = "0x04"
register "ssdb.rom_type" = "0x08"
register "ssdb.vcm_type" = "0x03"
register "ssdb.platform" = "0x09"
register "ssdb.flash_support" = "0x02"
register "ssdb.privacy_led" = "0x01"
register "ssdb.degree" = "0x00"
register "ssdb.mipi_define" = "0x01"
register "ssdb.mclk" = "0x016E3600"
# Sensor PWDB entries
register "num_pwdb_entries" = "5"
register "pwdb[0].name" = ""VSIO""
register "pwdb[0].value" = "1800600"
register "pwdb[0].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[0].delay_usec" = "0"
register "pwdb[1].name" = ""tps68470-a""
register "pwdb[1].value" = "19200000"
register "pwdb[1].entry_type" = "INTEL_ACPI_CAMERA_CLK"
register "pwdb[1].delay_usec" = "0"
register "pwdb[2].name" = ""ANA""
register "pwdb[2].value" = "2815200"
register "pwdb[2].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[2].delay_usec" = "3000"
register "pwdb[3].name" = ""s_resetn""
register "pwdb[3].value" = "1"
register "pwdb[3].entry_type" = "INTEL_ACPI_CAMERA_GPIO"
register "pwdb[3].delay_usec" = "0"
register "pwdb[4].name" = ""CORE""
register "pwdb[4].value" = "1200000"
register "pwdb[4].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[4].delay_usec" = "3000"
device i2c 10 on end
end
chip drivers/intel/mipi_camera
register "acpi_hid" = ""DW9714""
register "acpi_name" = ""VCM0""
register "chip_name" = ""Dongwoon AF DAC""
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
# VCM PWDB entries
register "num_pwdb_entries" = "2"
register "pwdb[0].name" = ""VSIO""
register "pwdb[0].value" = "1800600"
register "pwdb[0].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[0].delay_usec" = "0"
register "pwdb[1].name" = ""VCM""
register "pwdb[1].value" = "2815200"
register "pwdb[1].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[1].delay_usec" = "3000"
device i2c 0xc on end
end
end # I2C #2
device pci 15.3 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOM50C1""
register "generic.desc" = ""WCOM Digitizer""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)"
register "hid_desc_reg_offset" = "0x1"
device i2c 0x9 on end
end
end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 off end # SATA
device pci 19.0 on end # UART #2
device pci 19.1 on
chip drivers/i2c/max98927
register "interleave_mode" = "1"
register "uid" = "0"
register "desc" = ""SSM4567 Right Speaker Amp""
register "name" = ""MAXR""
device i2c 39 on end
end
chip drivers/i2c/max98927
register "interleave_mode" = "1"
register "uid" = "1"
register "desc" = ""SSM4567 Left Speaker Amp""
register "name" = ""MAXL""
device i2c 3A on end
end
chip drivers/i2c/generic
register "hid" = ""10EC5663""
register "name" = ""RT53""
register "desc" = ""Realtek RT5663""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
register "probed" = "1"
device i2c 13 on end
end
end # I2C #5
device pci 19.2 on
chip drivers/intel/mipi_camera
register "acpi_hid" = ""INT3479""
register "acpi_name" = ""CAM1""
register "chip_name" = ""OV 5670 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
# Camera SSDB buffer
register "ssdb.sensor_card_sku" = "0x50"
register "ssdb.link_used" = "0x01"
register "ssdb.lanes_used" = "0x02"
register "ssdb.rom_type" = "0x08"
register "ssdb.vcm_type" = "0x03"
register "ssdb.platform" = "0x09"
register "ssdb.flash_support" = "0x02"
register "ssdb.privacy_led" = "0x01"
register "ssdb.mipi_define" = "0x01"
register "ssdb.mclk" = "0x016E3600"
# Sensor PWDB entries
register "num_pwdb_entries" = "6"
register "pwdb[0].name" = ""VSIO""
register "pwdb[0].value" = "1800600"
register "pwdb[0].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[0].delay_usec" = "0"
register "pwdb[1].name" = ""AUX2""
register "pwdb[1].value" = "1800600"
register "pwdb[1].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[1].delay_usec" = "0"
register "pwdb[2].name" = ""tps68470-b""
register "pwdb[2].value" = "19200000"
register "pwdb[2].entry_type" = "INTEL_ACPI_CAMERA_CLK"
register "pwdb[2].delay_usec" = "0"
register "pwdb[3].name" = ""gpio.4""
register "pwdb[3].value" = "1"
register "pwdb[3].entry_type" = "INTEL_ACPI_CAMERA_GPIO"
register "pwdb[3].delay_usec" = "3000"
register "pwdb[4].name" = ""gpio.5""
register "pwdb[4].value" = "1"
register "pwdb[4].entry_type" = "INTEL_ACPI_CAMERA_GPIO"
register "pwdb[4].delay_usec" = "0"
register "pwdb[5].name" = ""AUX1""
register "pwdb[5].value" = "1213200"
register "pwdb[5].entry_type" = "INTEL_ACPI_CAMERA_REGULATOR"
register "pwdb[5].delay_usec" = "3000"
device i2c 10 on end
end
end # I2C #4
device pci 1c.0 on
chip drivers/intel/wifi
register "wake" = "GPE0_PCI_EXP"
device pci 00.0 on end
end
end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard
device pci 1f.0 on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end
end