merge latest quartet changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
e4436bd7f6
commit
888df97971
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@ -15,6 +15,9 @@ uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE 524288
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###
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### Build options
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###
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@ -68,9 +71,6 @@ option MAINBOARD_VENDOR="AMD"
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### LinuxBIOS layout values
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###
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE = 524288
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE = 65536
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@ -159,7 +159,7 @@ makerule ./auto.E
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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end
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##
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@ -229,32 +229,30 @@ northbridge amd/amdk8 "mc0"
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131"
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111"
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pci 0:0.0
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pci 0:1.0
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pci 0:1.1
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pci 0:1.2
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pci 0:1.3
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pci 0:1.5
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pci 0:1.6
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superio NSC/pc87360
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pnp 1:2e.0
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pnp 1:2e.1
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pnp 1:2e.2
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pnp 1:2e.3
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pnp 1:2e.4
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pnp 1:2e.5
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pnp 1:2e.6
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pnp 1:2e.7
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pnp 1:2e.8
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pnp 1:2e.9
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pnp 1:2e.a
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southbridge amd/amd8111 "amd8111" link 2
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pci 0:0.0 on
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pci 0:1.0 on
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pci 0:1.1 on
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pci 0:1.2 on
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pci 0:1.3 on
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pci 0:1.5 on
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pci 0:1.6 on
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pci 1:0.0 on
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 on
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superio NSC/pc87360 link 1
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pnp 2e.0
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pnp 2e.1
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pnp 2e.2
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pnp 2e.3
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pnp 2e.4
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pnp 2e.5
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pnp 2e.6
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pnp 2e.7
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pnp 2e.8
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pnp 2e.9
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pnp 2e.a
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register "com1" = "{1, 0, 0x3f8, 4}"
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register "lpt" = "{1}"
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end
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@ -268,6 +266,18 @@ northbridge amd/amdk8 "mc1"
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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southbridge amd/amd8131 "amd8131" link 1
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8131 "amd8131" link 1
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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end
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northbridge amd/amdk8 "mc2"
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@ -289,7 +299,6 @@ northbridge amd/amdk8 "mc3"
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end
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cpu k8 "cpu0"
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register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
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end
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cpu k8 "cpu1"
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@ -19,25 +19,32 @@
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#define SIO_BASE 0x2e
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 30);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 31);
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}
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else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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}
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}
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/*
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@ -110,9 +117,6 @@ static void coherent_ht_mainboard(unsigned cpus)
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{
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}
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#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#define CONNECTION_0_1 UP
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@ -272,8 +276,21 @@ static void main(void)
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#endif
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#if 0
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ram_check(0x00000000, msr.lo);
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#else
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/* Check 16MB of memory */
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ram_check(0x00000000, 0x01000000);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if 0
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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}
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@ -27,6 +27,10 @@ static void main(void)
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asm("jmp __cpu_reset");
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}
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}
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/* Is this a deliberate reset by the bios */
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else if (bios_reset_detected() && last_boot_normal()) {
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asm("jmp __normal_image");
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}
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/* Is this a secondary cpu? */
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else if (!boot_cpu() && last_boot_normal()) {
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asm("jmp __normal_image");
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@ -1,43 +1,34 @@
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*18, /* there can be total 18 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0x23, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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32+16*9, /* there can be total 9 devices on the bus */
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1, /* Where the interrupt router lies (bus) */
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(4<<3)|3, /* Where the interrupt router lies (dev) */
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0x0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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{0,0x50, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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{0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x3, 0},
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{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
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{0x1,0x18, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
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{0x1,0x20, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
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{0x2,0x28, {{0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xa, 0},
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{0,0x58, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
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{0x3,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
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{0x3,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x9, 0},
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{0,0x30, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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{0x1,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
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{0x1,0x28, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
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{0x1,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x6, 0},
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{0x1,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xb, 0},
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{0,0x38, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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0xb0, /* u8 checksum , mod 256 checksum must give zero */
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{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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/* PCI Slot 1 */
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{0x03, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x01, 0},
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/* PCI Slot 2 */
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{0x03, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x02, 0},
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/* PCI Slot 3 */
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{0x02, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x03, 0},
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/* PCI Slot 4 */
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{0x02, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x04, 0},
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/* PCI Slot 5 */
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{0x04, (0x05<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x05, 0},
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/* PCI Slot 6 */
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{0x04, (0x04<<3)|0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x06, 0},
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/* Onboard NICS */
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{0x02, (0x03<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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{0x02, (0x04<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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/* Let Linux know about bus 1 */
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{0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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}
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};
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@ -48,8 +48,8 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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else {
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printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
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bus_8111_1 = 3;
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bus_isa = 4;
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bus_8111_1 = 4;
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bus_isa = 5;
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}
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/* 8131-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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@ -60,7 +60,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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else {
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printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
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bus_8131_1 = 1;
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bus_8131_1 = 2;
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}
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/* 8131-2 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
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@ -71,7 +71,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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else {
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printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_8131_2 = 2;
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bus_8131_2 = 3;
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}
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}
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@ -144,10 +144,6 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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bus_isa, 0x00, MP_APIC_ALL, 0x01);
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/* AGP Slot */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, (6<<2)|0, 0x02, 0x12);
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/* PCI Slot 1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|0, 0x02, 0x11);
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