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VX900: Add support for early romstage 

Add support for VX900 early initialization up until, but not including
raminit. Add the basic infrastructure, add a romstrap table, and
functionality to configure the CPU bus and SMBus.

This code is necessary and sufficient to prepare us for raminit.

Change-Id: Icc9c41e4927b589f17416836f87a6a5843b24aa7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3372
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2013-06-04 23:37:56 -05:00 committed by Ronald G. Minnich
parent ee2bc27dc5
commit 88a302346f
12 changed files with 778 additions and 0 deletions
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1
src/northbridge/via/Kconfig
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@ -4,3 +4,4 @@ source src/northbridge/via/cn400/Kconfig
source src/northbridge/via/vt8601/Kconfig
source src/northbridge/via/vt8623/Kconfig
source src/northbridge/via/vx800/Kconfig
source src/northbridge/via/vx900/Kconfig

1
src/northbridge/via/Makefile.inc
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@ -4,4 +4,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400
subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800
subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX900) += vx900

41
src/northbridge/via/vx900/Kconfig Normal file
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@ -0,0 +1,41 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
##
config NORTHBRIDGE_VIA_VX900
bool
select IOAPIC
select DRIVERS_GENERIC_IOAPIC
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select GFXUMA
config MAX_PIRQ_LINKS
int
default 8
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config VGA_BIOS_ID
string
default "1106,7122"

37
src/northbridge/via/vx900/Makefile.inc Normal file
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@ -0,0 +1,37 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011-2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
##
romstage-y += pci_util.c
romstage-y += early_smbus.c
romstage-y += early_vx900.c
romstage-y += early_host_bus_ctl.c
#romstage-y += raminit_ddr3.c
romstage-y += ./../../../device/dram/ddr3.c
romstage-y += ./../../../southbridge/via/common/early_smbus_delay.c
romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c
romstage-y += ./../../../southbridge/via/common/early_smbus_print_error.c
romstage-y += ./../../../southbridge/via/common/early_smbus_reset.c
romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c
romstage-y += ./../../../drivers/pc80/udelay_io.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += ./../../../lib/cbmem.c
chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds

69
src/northbridge/via/vx900/early_host_bus_ctl.c Normal file
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@ -0,0 +1,69 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "early_vx900.h"
static void vx900_cpu_bus_preram_setup(void)
{
/* Faster CPU to DRAM Cycle */
pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08);
/* CPU Interface Control – Basic Options */
pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c);
/*CPU Interface Control – Advanced Options */
pci_write_config8(HOST_BUS, 0x52, 0xc7);
/* Enable 8QW burst and 4QW request merging [4] and [2]
* and special mode for read cycles bit[3] */
pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 4) | (1 << 2) | (1 << 3));
/* High priority upstream requests on V4 bus */
pci_write_config8(HOST_BUS, 0x56, 0x03);
/* CPU to DRAM extra 1T access control */
pci_mod_config8(HOST_BUS, 0x59, 0x00, (1 << 2));
/* Queue reordering */
pci_mod_config8(HOST_BUS, 0x5f, 0x00, (1 << 6));
/* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */
pci_mod_config8(HOST_BUS, 0x98, 0x00, 0x60);
/* 1T delay for data on CPU bus */
pci_write_config8(HOST_BUS, 0x9e, 0x0e);
/* Arbitrate ownership of DRAM controller a few cycles earlier */
pci_mod_config8(HOST_BUS, 0x9f, 0x00, (1 << 7));
/* Write retire policy */
pci_write_config8(HOST_BUS, 0x5d, 0xa2);
/* Occupancy timer */
pci_write_config8(HOST_BUS, 0x53, 0x44);
/* Medium Threshold for Write Retire Policy - 6 requests */
pci_mod_config8(HOST_BUS, 0x56, 0x00, 0x60);
/* Bandwidth timer */
pci_write_config8(HOST_BUS, 0x5e, 0x44);
}
/**
* \brief Configure the CPU to northbridge bus (formerly, FSB)
*
* Configure the CPU <-> host interface. This interface is complex and needs to
* be set up to operate properly. Configured parameters include bandwidth
* arbitration. This function does not, however, change the physical interface
* parameters, such as drive strength and signal timing. Instead, it assumes
* that those parameters were already configured correctly from the ROMSTRAP.
*/
void vx900_cpu_bus_interface_setup(void)
{
vx900_cpu_bus_preram_setup();
dump_pci_device(HOST_BUS);
}

194
src/northbridge/via/vx900/early_smbus.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <device/pci_ids.h>
#include "early_vx900.h"
#include <device/early_smbus.h>
#include <arch/io.h>
#include <console/console.h>
/**
* \brief SMBUS IO ports in relation to the base IO port
*/
#define SMBHSTSTAT(base) (u16)(u32)base + 0x0
#define SMBSLVSTAT(base) (u16)(u32)base + 0x1
#define SMBHSTCTL(base) (u16)(u32)base + 0x2
#define SMBHSTCMD(base) (u16)(u32)base + 0x3
#define SMBXMITADD(base) (u16)(u32)base + 0x4
#define SMBHSTDAT0(base) (u16)(u32)base + 0x5
#define SMBHSTDAT1(base) (u16)(u32)base + 0x6
#define SMBBLKDAT(base) (u16)(u32)base + 0x7
#define SMBSLVCTL(base) (u16)(u32)base + 0x8
#define SMBTRNSADD(base) (u16)(u32)base + 0x9
#define SMBSLVDATA (base) (u16)(u32)base + 0xa
static void smbus_delays(int delays)
{
while (delays--)
smbus_delay();
}
/**
* Read a byte from the SMBus.
*
* @param dimm The address location of the DIMM on the SMBus.
* @param offset The offset the data is located at.
*/
u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
{
u8 val;
/* Initialize SMBUS sequence */
smbus_reset(smbus_dev);
/* Clear host data port. */
outb(0x00, SMBHSTDAT0(smbus_dev));
smbus_wait_until_ready(smbus_dev);
smbus_delays(50);
/* Actual addr to reg format. */
addr = (addr << 1);
addr |= 1; /* read command */
outb(addr, SMBXMITADD(smbus_dev));
outb(offset, SMBHSTCMD(smbus_dev));
/* Start transaction, byte data read. */
outb(0x48, SMBHSTCTL(smbus_dev));
smbus_wait_until_ready(smbus_dev);
val = inb(SMBHSTDAT0(smbus_dev));
return val;
}
void enable_smbus(void)
{
device_t dev;
u8 reg8;
u32 smbus_dev = (u32) SMBUS_IO_BASE;
/* Locate the Power Management control */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_LPC), 0);
if (dev == PCI_DEV_INVALID) {
die("Power Management Controller not found\n");
}
/*
* To use SMBus to manage devices on the system board, it is a must to
* enable SMBus function by setting
* PMU_RXD2[0] (SMBus Controller Enable) to 1.
* And set PMU_RXD0 and PMU_RXD1 (SMBus I/O Base) to an appropriate
* I/O port address, so that all registers in SMBus I/O port can be
* accessed.
*/
reg8 = pci_read_config8(dev, 0xd2);
/* Enable SMBus controller */
reg8 |= 1;
/* Set SMBUS clock from 128k source */
reg8 |= 1 << 2;
pci_write_config8(dev, 0xd2, reg8);
reg8 = pci_read_config8(dev, 0x94);
/* SMBUS clock from divider of 14.318 MHz */
reg8 &= ~(1 << 7);
pci_write_config8(dev, 0x94, reg8);
/* Set SMBus IO base */
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE);
/*
* Initialize the SMBus sequence:
*/
/* Clear SMBus host status register */
smbus_reset(smbus_dev);
/* Clear SMBus host data 0 register */
outb(0x00, SMBHSTDAT0(smbus_dev));
/* Wait for SMBUS */
smbus_wait_until_ready(smbus_dev);
}
static int spd_get_length(u8 spd_byte0)
{
spd_byte0 &= 0xf;
switch (spd_byte0) {
case 0x3:
return 256;
case 0x2:
return 176;
case 0x1:
return 128;
default:
break;
}
return 0;
}
void spd_read(u8 addr, spd_raw_data spd)
{
u8 reg;
int i, regs;
u32 smbus_dev = SMBUS_IO_BASE;
reg = smbus_read_byte(smbus_dev, addr, 2);
if (reg != 0x0b) {
printk(BIOS_DEBUG, "SMBUS device %x not a DDR3 module\n", addr);
spd[2] = 0;
return;
}
reg = smbus_read_byte(smbus_dev, addr, 0);
if ((regs = spd_get_length(reg)) == 0) {
printk(BIOS_INFO, "No DIMM present at %x\n", addr);
spd[2] = 0;
return;
}
for (i = 0; i < regs; i++)
spd[i] = smbus_read_byte(smbus_dev, addr, i);
}
void dump_spd_data(spd_raw_data spd)
{
int len, i;
u8 reg;
if ((len = spd_get_length(spd[0])) == 0) {
printk(BIOS_DEBUG, "Invalid SPD\n");
return;
}
/*
* I originally saw this way to present SPD data in code from VIA. I
* really liked the idea, so here it goes.
*/
print_debug(" 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n");
print_debug("---+------------------------------------------------");
for (i = 0; i < len; i++) {
reg = spd[i];
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%.2x |", i);
printk(BIOS_DEBUG, " %.2x", reg);
}
print_debug("\n");
}

145
src/northbridge/via/vx900/early_vx900.c Normal file
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@ -0,0 +1,145 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "early_vx900.h"
#include <arch/io.h>
#include <console/console.h>
unsigned long get_top_of_ram(void)
{
u16 reg_tom = pci_read_config8(MCU, 0x88);
return (((unsigned long)reg_tom) << 24) - (256 << 20);
}
struct cbmem_entry *get_cbmem_toc(void)
{
return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
}
/**
* \brief Enable accessing of PCI configuration space for all devices.
*
* Enable accessing of D0F1 through D0F7, which would otherwise not be
* accessible. If MMCONF is enabled, configure it here. This is the first
* function that should be called in romstage.
*/
void vx900_enable_pci_config_space(void)
{
/* MMCONF is not yet enabled, so we'll need to specify we want to do
* pci_io. We don't want to do pci_mmio until we enable it */
/* Enable multifunction bit for northbridge.
* This enables the PCI configuration spaces of D0F1 to D0F7 to be
* accessed */
pci_io_write_config8(HOST_CTR, 0x4f, 0x01);
#if CONFIG_MMCONF_SUPPORT
/* COOL, now enable MMCONF */
u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60);
reg8 |= 3;
pci_io_write_config8(TRAF_CTR, 0x60, reg8);
reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28;
pci_io_write_config8(TRAF_CTR, 0x61, reg8);
#endif
}
/**
*\brief Prints information regarding the hardware strapping on VX900
*
* Certain features on the VX900 are controlled by strapping pins which are
* hardwired on the mainboard. These values determine whether the ROM is on the
* SPI or LPC bus, or whether auto-reset is enabled.
* \n
* Having a feel for these values is important when trying to fix obscure
* problems found when porting a mainboard based on the VX900.
* \n
* These values are decoded and printed to the terminal.
*/
void vx900_print_strapping_info(void)
{
u8 strap = pci_read_config8(SNMIC, 0x56);
print_debug("VX900 strapping pins indicate that:\n");
printk(BIOS_DEBUG, " ROM is on %s bus\n",
(strap & (1 << 0)) ? "SPI" : "LPC");
printk(BIOS_DEBUG, " Auto reset is %s\n",
(strap & (1 << 1)) ? "disabled" : "enabled");
printk(BIOS_DEBUG, " LPC FWH command is %s\n",
(strap & (1 << 2)) ? "enabled" : "disabled");
printk(BIOS_DEBUG, " Debug link is is %s\n",
(strap & (1 << 4)) ? "enabled" : "disabled");
printk(BIOS_DEBUG, " PCI master mode is %s\n",
(strap & (1 << 5)) ? "enabled" : "disabled");
}
/**
*\brief Disables the auto-reboot mechanism on VX900
*
* The VX900 has an auto-reboot mechanism that can be enabled by a hardware
* strap. This mechanism can make development annoying, since we don't know if
* the reset was caused by a bug in coreboot, or by this mechanism.
*/
void vx900_disable_auto_reboot(void)
{
if (pci_read_config8(SNMIC, 0x56) & (1 << 1)) {
print_debug("Auto-reboot is disabled in hardware\n");
return;
}
/* Disable the GP3 timer, which is the root of all evil */
pci_write_config8(LPC, 0x98, 0);
/* Yep, that's all it takes */
print_debug("GP3 timer disabled."
" Auto-reboot should not give you any more trouble.\n");
}
/**
* \brief Disables 'shadowing' of system ROM
*
* Disable unnecessary shadowing of the ROM in the first 1MB of address space.
* Coreboot runs in 32-bit mode from the start. Shadowing only gets in the way.
* This function frees the entire 640k-1M range for DRAM. VGA may still use
* the 640k-768k range, if enabled later.
*/
void vx900_disable_legacy_rom_shadow(void)
{
pci_write_config8(MCU, 0x80, 0xff); /* LPC ROM 768k - 832k */
pci_write_config8(MCU, 0x81, 0xff); /* LPC ROM 832k - 896k */
pci_write_config8(MCU, 0x82, 0xff); /* LPC ROM 896k - 960k */
/* LPC ROM 960k - 1M * SMRAM: 640k - 768k */
pci_write_config8(MCU, 0x83, 0x31);
/* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */
pci_mod_config8(LPC, 0x41, 1 << 7, 0); /* LPC ROM 896k - 960k */
pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */
pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */
pci_write_config8(SNMIC, 0x63, 0); /* 896k - 1M */
pci_write_config8(SNMIC, 0x64, 0); /* 896k - 960k */
}
/**
* \brief Disables the VX900 integrated graphics controller
*
* Disable the graphics controller entirely. It will no longer be visible as a
* PCI device.
*/
void vx900_disable_gfx(void)
{
/* Disable GFX */
pci_mod_config8(MCU, 0xa1, 1 << 7, 0);
}

81
src/northbridge/via/vx900/early_vx900.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef EARLY_VX900_H
#define EARLY_VX900_H
#include "raminit.h"
#include "vx900.h"
#include <arch/io.h>
#include <cbmem.h>
#include <stdint.h>
#include <arch/io.h>
/* North Module devices */
#define HOST_CTR PCI_DEV(0, 0, 0)
#define ERR_REP PCI_DEV(0, 0, 1)
#define HOST_BUS PCI_DEV(0, 0, 2)
#define MCU PCI_DEV(0, 0, 3)
#define POWERMAN PCI_DEV(0, 0, 4)
#define TRAF_CTR PCI_DEV(0, 0, 5)
#define NSBIC PCI_DEV(0, 0, 7)
#define GFX PCI_DEV(0, 1, 0)
#define HDMI PCI_DEV(0, 1, 0)
#define PEXx PCI_DEV(0, 3, x)
#define PEX_CTR PCI_DEV(0, 3, 4)
/* South Module devices */
#define UARTx PCI_DEV(0, 0x0a, x)
#define USB_MASS PCI_DEV(0, 0x0b, 0)
#define SDIO PCI_DEV(0, 0x0c, 0)
#define CARD_RD PCI_DEV(0, 0x0d, 0)
#define SATA PCI_DEV(0, 0x0d, 0)
#define USBx PCI_DEV(0, 0x10, x)
#define USB_EHCI PCI_DEV(0, 0x10, 4)
#define LPC PCI_DEV(0, 0x11, 0)
#define PMU LPC
#define SNMIC PCI_DEV(0, 0x11, 7)
#define P2P PCI_DEV(0, 0x13, 0)
#define HDAC PCI_DEV(0, 0x14, 0)
/* These control the behavior of raminit */
#define RAMINIT_USE_HW_RXCR_CALIB 0
#define RAMINIT_USE_HW_MRS_SEQ 0
unsigned long get_top_of_ram(void);
void enable_smbus(void);
void dump_spd_data(spd_raw_data spd);
void spd_read(u8 addr, spd_raw_data spd);
void vx900_enable_pci_config_space(void);
void vx900_disable_legacy_rom_shadow(void);
void vx900_print_strapping_info(void);
void vx900_disable_auto_reboot(void);
void vx900_cpu_bus_interface_setup(void);
void vx900_dram_set_gfx_resources(void);
void vx900_disable_gfx(void);
#endif /* EARLY_VX900_H */

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src/northbridge/via/vx900/pci_util.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "vx900.h"
void dump_pci_device(device_t dev)
{
int i;
for (i = 0; i <= 0xff; i++) {
unsigned char val;
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%.2x:", i);
if ((i & 0x0f) == 0x08)
printk(BIOS_DEBUG, " |");
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %.2x", val);
if ((i & 0x0f) == 0x0f)
printk(BIOS_DEBUG, "\n");
}
}
void pci_mod_config8(device_t dev, unsigned int where,
uint8_t clr_mask, uint8_t set_mask)
{
uint8_t reg8 = pci_read_config8(dev, where);
reg8 &= ~clr_mask;
reg8 |= set_mask;
pci_write_config8(dev, where, reg8);
}
void pci_mod_config16(device_t dev, unsigned int where,
uint16_t clr_mask, uint16_t set_mask)
{
uint16_t reg16 = pci_read_config16(dev, where);
reg16 &= ~clr_mask;
reg16 |= set_mask;
pci_write_config16(dev, where, reg16);
}
void pci_mod_config32(device_t dev, unsigned int where,
uint32_t clr_mask, uint32_t set_mask)
{
uint32_t reg32 = pci_read_config32(dev, where);
reg32 &= ~clr_mask;
reg32 |= set_mask;
pci_write_config32(dev, where, reg32);
}

60
src/northbridge/via/vx900/romstrap.inc Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Tyan Computer
* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer)
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2009 One Laptop per Child, Association, Inc.
* Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* As extracted from the manufacturer's ROM, the romstrap table looks like:
* .long 0x77886047 .long 0x00777777
* .long 0x00000000 .long 0x00000000
* .long 0x00888888 .long 0x00AA1111
* .long 0x00000000 .long 0x00000000
*
* The vendor BIOS then adjusts some of these settings very early on. Instead of
* adjusting those settings in code, we work them in the romstrap table.
*
*/
/* This file constructs the ROM strap table for VX900 */
.section ".romstrap", "a", @progbits
.globl __romstrap_start
__romstrap_start:
tblpointer:
.long 0x77886047
.long 0x00777777
.long 0x00000000
.long 0x00000000
.long 0x00888888
.long 0x00AA1111
.long 0x00000000
.long 0x00000000
/*
* The pointer to above table should be at 0xffffffd0,
* the table itself MUST be aligned to 128B it seems!
*/
rspointers:
.long tblpointer // It will be 0xffffffd0
.globl __romstrap_end
__romstrap_end:
.previous

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src/northbridge/via/vx900/romstrap.lds Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 AMD
* (Written by Yinghai Lu <yinghai.lu@amd.com> for AMD)
* Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>
*/
SECTIONS {
. = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start);
.romstrap (.): {
*(.romstrap)
}
}

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src/northbridge/via/vx900/vx900.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __VX900_H
#define __VX900_H
#define VX900_ACPI_IO_BASE 0x0400
#define VX900_NB_IOAPIC_ID 0x2
#define VX900_NB_IOAPIC_BASE 0xfecc000
#define VX900_SB_IOAPIC_ID 0x1
#define VX900_SB_IOAPIC_BASE 0xfec0000
#define SMBUS_IO_BASE 0x500
/* The maximum number of DIMM slots that the VX900 supports */
#define VX900_MAX_DIMM_SLOTS 2
#define VX900_MAX_MEM_RANKS 4
#define min(a,b) a<b?a:b
#define max(a,b) a>b?a:b
#include <arch/io.h>
#include <device/pci.h>
#include <console/console.h>
u32 chrome9hd_fb_size(void);
/* We use these throughout the code. They really belong in a generic part of
* coreboot, but until bureaucracy gets them there, we still need them */
void dump_pci_device(device_t dev);
void pci_mod_config8(device_t dev, unsigned int where,
uint8_t clr_mask, uint8_t set_mask);
void pci_mod_config16(device_t dev, unsigned int where,
uint16_t clr_mask, uint16_t set_mask);
void pci_mod_config32(device_t dev, unsigned int where,
uint32_t clr_mask, uint32_t set_mask);
#endif /* __VX900_H */