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soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence 

This patch provides a workaround which skips requesting IOM for D3 cold
entry sequence.

BUG=b:244082753
TEST=Verified MUX configuration after hot plugging Type-C devices on
Rex and MTL RVP boards.

Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
zhaojohn 2022-09-12 14:24:59 -07:00 committed by Tim Wawrzynczak
parent a0e36d8cba
commit 88a496a9c8
1 changed files with 7 additions and 1 deletions
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8
src/soc/intel/meteorlake/acpi/tcss.asl
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@ -719,7 +719,13 @@ Scope (\_SB.PCI0)
} }
/* Request IOM for D3 cold entry sequence. */ /* Request IOM for D3 cold entry sequence. */
TD3C = 1 /*
* FIXME: Remove this workaround after resolving b/244082753
*
* Document #742990: TCCold exit flow may not complete when processor at package
* C0. The implication is that the system may hang.
*/
// TD3C = 1
} }
PowerResource (D3C, 5, 0) PowerResource (D3C, 5, 0)