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soc/amd/picassso/acpi: increase MMIO region size of GPIO controller 

The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.

Also replace the base GPIO address with the corresponding define.

Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2020-12-03 18:17:57 +01:00
parent ce66f34372
commit 88d8e2b74e
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/picasso/acpi/sb_fch.asl
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@ -34,7 +34,7 @@ Device (GPIO)
ActiveLow,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
}
CreateDWordField (Local0, IRQR._INT, IRQN)
If (PMOD) {
@ -44,7 +44,7 @@ Device (GPIO)
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
})
} Else {
Return (Local0)