fixes for EPIA.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -37,7 +37,7 @@ static void early_mtrr_init(void)
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const unsigned long *msr_addr;
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unsigned long cr0;
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print_err("Disabling cache\n");
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print_err("Disabling cache\r\n");
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/* Just to be sure, take all the steps to disable the cache.
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* This may not be needed, but C3's may...
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* Invalidate the cache */
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@ -56,7 +56,7 @@ static void early_mtrr_init(void)
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/* Invalidate the cache again */
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asm volatile ("invd");
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print_err("Clearing mtrr\n");
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print_err("Clearing mtrr\r\n");
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/* Inialize all of the relevant msrs to 0 */
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msr.lo = 0;
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@ -81,7 +81,7 @@ static void early_mtrr_init(void)
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wrmsr(0x201, msr);
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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print_err("Setting XIP\n");
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print_err("Setting XIP\r\n");
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/* enable write through caching so we can do execute in place
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* on the flash rom.
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*/
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@ -104,5 +104,5 @@ static void early_mtrr_init(void)
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cr0 = read_cr0();
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cr0 &= 0x9fffffff;
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write_cr0(cr0);
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print_err("Enabled the cache\n");
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print_err("Enabled the cache\r\n");
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}
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@ -50,12 +50,6 @@ object irq_tables.o
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##
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option HAVE_OPTION_TABLE=1
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER="HDAMA"
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option MAINBOARD_VENDOR="ARIMA"
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###
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### LinuxBIOS layout values
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###
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@ -137,7 +131,7 @@ end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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action "./romcc -O2 -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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@ -146,7 +140,7 @@ makerule ./auto.E
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -O ./auto.E > auto.inc"
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action "./romcc -O2 -mcpu=c3 ./auto.E > auto.inc"
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end
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##
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@ -1,5 +1,7 @@
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#define ASSEMBLY 1
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#define MAXIMUM_CONSOLE_LOGLEVEL 6
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#define DEFAULT_CONSOLE_LOGLEVEL 6
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#include <stdint.h>
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#include <device/pci_def.h>
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@ -27,8 +29,6 @@ void udelay(int usecs)
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#include "southbridge/via/vt8231/vt8231_early_smbus.c"
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#define MAXIMUM_CONSOLE_LOGLEVEL 6
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#define DEFAULT_CONSOLE_LOGLEVEL 6
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#include "southbridge/via/vt8231/vt8231_early_serial.c"
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static void memreset_setup(void)
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@ -455,11 +455,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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// for(i = 0; i < 8; i++)
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base = do_module_size(0); /*, base);*/
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pci_write_config8(north, ramregs[0], base);
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base = do_module_size(1); /*, base);*/
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base += pci_read_config8(north, ramregs[0]);
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base += do_module_size(1); /*, base);*/
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pci_write_config8(north, ramregs[1], base);
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/* runs out of code space. */
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for(i = 0; i < 8; i++){
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for(i = 2; i < 8; i++){
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pci_write_config8(north, ramregs[i], base);
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/*
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pci_write_config8(north, ramregs[3], base);
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@ -437,7 +437,6 @@ static void southbridge_init(struct chip *chip, enum chip_pass pass)
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case CONF_PASS_POST_PCI:
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vt8231_init(conf);
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printk_err("FUCK! ROUTING FIXUP!\n");
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pci_routing_fixup();
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break;
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@ -47,8 +47,8 @@ static void enable_smbus(void)
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c = pci_read_config8(dev, 4);
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c |= 1;
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pci_write_config8(dev, 4, c);
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print_err_hex8(c);
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print_err(" is the comm register\n");
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print_debug_hex8(c);
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print_debug(" is the comm register\r\n");
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print_debug("SMBus controller enabled\r\n");
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}
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@ -69,9 +69,9 @@ static int smbus_wait_until_ready(void)
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smbus_delay();
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c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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while((c & 1) == 1) {
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print_err("c is ");
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print_err_hex8(c);
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print_err("\n");
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print_debug("c is ");
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print_debug_hex8(c);
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print_debug("\r\n");
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c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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/* nop */
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}
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@ -88,9 +88,9 @@ void smbus_reset(void)
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outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
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smbus_wait_until_ready();
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print_err("After reset status ");
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print_err_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
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print_err("\n");
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print_debug("After reset status ");
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print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
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print_debug("\r\n");
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}
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@ -117,21 +117,21 @@ static void smbus_print_error(unsigned char host_status_register)
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print_err("smbus_error: ");
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print_err_hex8(host_status_register);
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print_err("\n");
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print_err("\r\n");
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if (host_status_register & (1 << 4)) {
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print_err("Interrup/SMI# was Failed Bus Transaction\n");
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print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
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}
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if (host_status_register & (1 << 3)) {
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print_err("Bus Error\n");
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print_err("Bus Error\r\n");
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}
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if (host_status_register & (1 << 2)) {
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print_err("Device Error\n");
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print_err("Device Error\r\n");
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}
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if (host_status_register & (1 << 1)) {
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print_err("Interrupt/SMI# was Successful Completion\n");
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print_err("Interrupt/SMI# was Successful Completion\r\n");
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}
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if (host_status_register & (1 << 0)) {
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print_err("Host Busy\n");
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print_err("Host Busy\r\n");
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}
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}
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