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AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port 

Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.

Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7602
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki 2014-11-21 17:40:37 +02:00
parent 8c20a04cae
commit 88ff8b541f
12 changed files with 26 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/amd/olivehill/agesawrapper.c
View File

@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

4
src/mainboard/amd/olivehill/romstage.c
View File

@ -53,6 +53,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {

7
src/mainboard/amd/parmer/agesawrapper.c
View File

@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

4
src/mainboard/amd/parmer/romstage.c
View File

@ -45,6 +45,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {

7
src/mainboard/amd/thatcher/agesawrapper.c
View File

@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

10
src/mainboard/amd/thatcher/romstage.c
View File

@ -46,13 +46,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
device_t dev;
pci_devfn_t dev;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
/* Set LPC decode enables. */
dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80();
//__asm__ volatile ("1: jmp 1b");
/* TODO: */
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);

7
src/mainboard/asrock/imb-a180/agesawrapper.c
View File

@ -133,8 +133,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@ -151,11 +149,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

4
src/mainboard/asrock/imb-a180/romstage.c
View File

@ -58,6 +58,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80();
/* Enable the AcpiMmio space */

7
src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
View File

@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

4
src/mainboard/hp/pavilion_m6_1035dx/romstage.c
View File

@ -41,6 +41,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {

7
src/mainboard/lenovo/g505s/agesawrapper.c
View File

@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

4
src/mainboard/lenovo/g505s/romstage.c
View File

@ -41,6 +41,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {