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mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride 

Disable the GpioOverride UPD in FSP M, and comment out the Clock Request
GPIOs to ensure that coreboot doesn't touch them.

This solves behaviour that can only be described as weird:
* Devices connected to Root Ports don't initialise
* Hang seen when entering S5
* Hang when edk2 is reached

Change-Id: Idf8d2112a1c44064af73bb54fd3e1a1a429e0649
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2023-09-21 09:27:47 +01:00 committed by Matt DeVillier
parent 53f4cafcca
commit 8902dfa2bd
4 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/starlabs/starbook/variants/adl/gpio.c
View File

@ -209,11 +209,11 @@ const struct pad_config gpio_table[] = {
/* D5: Not Connected */
PAD_NC(GPP_D5, NONE),
/* D6: Clock Request 1 PCH M.2 SSD */
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
// PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
/* D7: Clock Request 2 Wireless LAN */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8: Clock Request 3 LAN */
PAD_NC(GPP_D8, NONE),
// PAD_NC(GPP_D8, NONE),
/* D9: GSPI 2 FPS */
PAD_NC(GPP_D9, NONE),
/* D10: GSPI 2 Clock */
@ -374,7 +374,7 @@ const struct pad_config gpio_table[] = {
/* H18: CPI C10 Gate */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19: Clock Request 4 CPU M.2 SSD */
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* H20: Not Connected */
PAD_NC(GPP_H20, NONE),
/* H21: Not Connected */

1
src/mainboard/starlabs/starbook/variants/adl/romstage.c
View File

@ -35,4 +35,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4);
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
};

8
src/mainboard/starlabs/starbook/variants/rpl/gpio.c
View File

@ -209,11 +209,11 @@ const struct pad_config gpio_table[] = {
/* D5: Not Connected */
PAD_NC(GPP_D5, NONE),
/* D6: Clock Request 1 PCH M.2 SSD */
PAD_NC(GPP_D6, NONE),
// PAD_NC(GPP_D6, NONE),
/* D7: Clock Request 2 Wireless LAN */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8: Clock Request 3 LAN */
PAD_NC(GPP_D8, NONE),
// PAD_NC(GPP_D8, NONE),
/* D9: GSPI 2 FPS */
PAD_NC(GPP_D9, NONE),
/* D10: GSPI 2 Clock */
@ -374,7 +374,7 @@ const struct pad_config gpio_table[] = {
/* H18: CPI C10 Gate */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19: Clock Request 4 CPU M.2 SSD */
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* H20: Not Connected */
PAD_NC(GPP_H20, NONE),
/* H21: Not Connected */

1
src/mainboard/starlabs/starbook/variants/rpl/romstage.c
View File

@ -44,4 +44,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
}
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
};