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nb/intel/gm45: Don't use PCI operations on the pci_domain device 

pci ops happen to work on this struct device since the device_path is an union.

This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.

Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27242
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-06-26 21:01:40 +02:00 committed by Felix Held
parent 15e1b39e6e
commit 8908931f1e
1 changed files with 11 additions and 7 deletions
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18
src/northbridge/intel/gm45/northbridge.c
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@ -96,16 +96,18 @@ static void mch_domain_read_resources(struct device *dev)
pci_domain_read_resources(dev); pci_domain_read_resources(dev);
struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
/* Top of Upper Usable DRAM, including remap */ /* Top of Upper Usable DRAM, including remap */
touud = pci_read_config16(dev, D0F0_TOUUD); touud = pci_read_config16(mch, D0F0_TOUUD);
touud <<= 20; touud <<= 20;
/* Top of Lower Usable DRAM */ /* Top of Lower Usable DRAM */
tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0;
tolud <<= 16; tolud <<= 16;
/* Top of Memory - does not account for any UMA */ /* Top of Memory - does not account for any UMA */
tom = pci_read_config16(dev, D0F0_TOM) & 0x1ff; tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff;
tom <<= 27; tom <<= 27;
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
@ -114,7 +116,7 @@ static void mch_domain_read_resources(struct device *dev)
tomk = tolud >> 10; tomk = tolud >> 10;
/* Graphics memory comes next */ /* Graphics memory comes next */
const u16 ggc = pci_read_config16(dev, D0F0_GGC); const u16 ggc = pci_read_config16(mch, D0F0_GGC);
if (!(ggc & 2)) { if (!(ggc & 2)) {
printk(BIOS_DEBUG, "IGD decoded, subtracting "); printk(BIOS_DEBUG, "IGD decoded, subtracting ");
@ -130,7 +132,7 @@ static void mch_domain_read_resources(struct device *dev)
uma_sizek = gms_sizek + gsm_sizek; uma_sizek = gms_sizek + gsm_sizek;
} }
const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC);
const u32 tseg_sizek = decode_tseg_size(esmramc); const u32 tseg_sizek = decode_tseg_size(esmramc);
printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10); printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10);
tomk -= tseg_sizek; tomk -= tseg_sizek;
@ -186,10 +188,12 @@ static void mch_domain_init(struct device *dev)
{ {
u32 reg32; u32 reg32;
struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(mch, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR; reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config32(mch, PCI_COMMAND, reg32);
} }
static const char *northbridge_acpi_name(const struct device *dev) static const char *northbridge_acpi_name(const struct device *dev)